公开(公告)号：BR9402107A

公开(公告)日：1994-12-13

申请号：BR9402107

申请日：1994-05-27

Applicant: IBM

Inventor： AMINI NADER ,  KOHLI ASHU

IPC: G06F13/12 ,  G06F13/42 ,  G06F13/36 ,  G06F13/38

公开(公告)号：CA2124032A1

公开(公告)日：1994-11-29

申请号：CA2124032

申请日：1994-05-20

Applicant: IBM

Inventor： AMINI NADER ,  KOHLI ASHU ,  SANTOS GREGORY N

IPC: G06F13/36 ,  G06F13/28 ,  G06F13/40

Abstract: BUS-TO-BUS BRIDGE FOR A MULTIPLE BUS INFORMATION HANDLING SYSTEM THAT OPTIMIZES DATA TRANSFERS BETWEEN A SYSTEM BUS AND A PERIPHERAL BUS The present invention provides hardware logic within a host bridge that connects a system bus to a peripheral bus using PCI bus architecture or a peripheral bus that uses a bus architecture similar to PCI. The inventive hardware optimizes the speed at which data transfers are accomplished between the buses while translating the data transfers between the different architectures of the two buses.

公开(公告)号：BR9402100A

公开(公告)日：1995-07-11

申请号：BR9402100

申请日：1994-05-27

Applicant: IBM

Inventor： AMINI NADER ,  KOHLI ASHU ,  SANTOS GREGORY N

IPC: G06F13/36 ,  G06F13/28 ,  G06F13/40 ,  G06F13/42

Abstract: The present invention provides hardware logic within a host bridge 20 that connects a system bus 36 to a peripheral bus 22 using PCI bus architecture or a peripheral bus that uses a bus architecture similar to PCI. The inventive hardware optimizes the speed at which data transfers are accomplished between the buses while translating the data transfers between the different architectures of the two buses.

公开(公告)号：CA2124614A1

公开(公告)日：1994-11-29

申请号：CA2124614

申请日：1994-05-30

Applicant: IBM

Inventor： AMINI NADER ,  KOHLI ASHU

IPC: G06F13/12 ,  G06F13/42 ,  G06F13/38

Abstract: METHOD AND APPARATUS FOR PROVIDING BACK-TO-BACK DATA TRANSFERS IN AN INFORMATION HANDLING SYSTEM HAVING A MULTIPLEXED BUS A device for generating back-to-back data transfers on a bus in an information handling system is disclosed. The inventive device includes a detector for determining whether a first address value and a second address are within a range, a first register connected to the detector for storing the first address until the device generates the second address, a second register connected to the detector for storing the range value, and a transfer state block for driving the second address on the peripheral bus without a turnaround cycle if the detector determines that the first and second addresses are within the range. Thus, back-to-back data transfers are provided.