公开(公告)号：SG44432A1

公开(公告)日：1997-12-19

申请号：SG1996000366

申请日：1992-12-22

Applicant: IBM

Inventor： ALDEREGULA ALFERDO ,  AMINI NADER ,  HORNE RICHARD LOUIS ,  LOHMAN TERENCE JOSEPH ,  TRAN CANG NGOC

IPC: G06F13/16 ,  G06F13/36

Abstract: A computer system is provided, comprising system memory and a memory controller for controlling access to system memory, a central processing unit electrically connected with the memory controller, and a bus interface unit electrically connected to the memory controller by a system bus and electrically connected to an input/output device by an input/output bus. The bus interface unit includes translation logic for temporarily storing, in response to a predetermined set of operating conditions, data transferred between the system bus and the input/output bus through the bus interface unit. The predetermined set of operating conditions occur when (i) the memory controller on behalf of the central processing unit writes data to the input/output device, or (ii) the memory controller on behalf of the central processing unit initiates a read or write cycle destined for the input/output device acting as a slave on the input/output bus, and the data bus width of the memory controller is greater than a corresponding data bus width of the input/output device.

公开(公告)号：AU663536B2

公开(公告)日：1995-10-12

申请号：AU2979292

申请日：1992-12-02

Applicant: IBM

Inventor： AMINI NADER ,  BOURY BECHARA FOUAD ,  BRANNON SHERWOOD ,  HORNE RICHARD LOUIS ,  LOHMAN TERENCE JOSEPH

IPC: G06F13/36 ,  G06F13/16 ,  G06F13/18 ,  G06F13/14

Abstract: A computer system is provided, comprising system memory and a memory controller for controlling access to system memory by means of a memory bus, a central processing unit electrically connected with the memory controller for reading and writing data to the system memory over the memory bus, a bus interface unit electrically connected with the memory controller by means of a system bus, and an input/output device electrically connected to the bus interface unit by an input/output bus. The memory controller incorporates logic for arbitrating between the central processing unit and the input/output device to determine which of the central processing unit and the input/output device should be granted access to the system memory through said memory bus. The bus interface unit incorporates logic for overriding the memory controller logic, in response to a series of predetermined operating conditions, and grant exclusive access to system memory to the input/output device.

公开(公告)号：NZ245344A

公开(公告)日：1995-09-26

申请号：NZ24534492

申请日：1992-12-02

Applicant: IBM

Inventor： AMINI NADER ,  BOURY BECHARA FOUAD ,  BRANNON SHERWOOD ,  HORNE RICHARD LOUIS ,  LOHMAN TERRENCE JOSEPH

IPC: G06F13/36 ,  G06F13/16 ,  G06F15/76

Abstract: A computer system is provided, comprising system memory and a memory controller for controlling access to system memory by means of a memory bus, a central processing unit electrically connected with the memory controller for reading and writing data to the system memory over the memory bus, a bus interface unit electrically connected with the memory controller by means of a system bus, and an input/output device electrically connected to the bus interface unit by an input/output bus. The memory controller incorporates logic for arbitrating between the central processing unit and the input/output device to determine which of the central processing unit and the input/output device should be granted access to the system memory through said memory bus. The bus interface unit incorporates logic for overriding the memory controller logic, in response to a series of predetermined operating conditions, and grant exclusive access to system memory to the input/output device.

公开(公告)号：CA2124618A1

公开(公告)日：1994-11-29

申请号：CA2124618

申请日：1994-05-30

Applicant: IBM

Inventor： AMINI NADER ,  YAMAUCHI KAZUSHI

IPC: G06F13/14 ,  G06F15/177 ,  G06F13/38

Abstract: METHOD AND APPARATUS FOR INITIALIZING MULTIPLE BUS NETWORKS IN AN INFORMATION HANDLING SYSTEM The present invention provides a program that creates a preliminary map of a multiple bus network used to connect peripheral devices to the central processing unit of an information handling system. This preliminary map is then used by configuration software of the information handling system to locate the peripheral devices in the multiple bus network to configure them. If the physical configuration of the multiple bus network should change in any way, the inventive program can make corresponding changes in the preliminary map without having to rewrite or change the program.

公开(公告)号：DE69421453T2

公开(公告)日：2000-05-18

申请号：DE69421453

申请日：1994-05-25

Applicant: IBM

Inventor： AMINI NADER ,  BLAND PATRICK MAURICE ,  BOURY BECHARA FOUAD ,  HOFMANN RICHARD GERARD ,  LOHMAN TERENCE JOSEPH

IPC: G06F13/28 ,  G06F13/30 ,  G06F13/36 ,  G06F13/40

Abstract: A direct memory access (DMA) support mechanism is provided for use in a computer system 10 which comprises (i) a central processing unit (CPU) 24 connected to system memory 32 by a first system bus 36, and a second system bus 16 connected to the CPU; (ii) a host bridge 20 connecting the second system bus to a peripheral bus 22; (iii) an input/output (I/O) bridge 78 connecting the peripheral bus to a standard I/O bus 92, the standard I/O bus having a plurality of standard I/O devices 90 attached thereto; and (v) arbitration logic 42 which functions in an arbitration mode for arbitrating between the plurality of standard I/O devices competing for access to the standard I/O bus, and in a grant mode wherein a selected standard I/O device is granted access to the standard I/O bus. The DMA support mechanism comprises a direct memory access (DMA) controller 40 for performing DMA cycles on behalf of the selected standard I/O device, and direct memory access (DMA) support logic for enabling the DMA cycles to be performed over the peripheral bus. The DMA support logic includes sideband signals directly connecting the DMA controller with the I/O bridge, the sideband signals including information identifying the bus size of the selected I/O device for which the DMA controller is performing the DMA cycles.

公开(公告)号：AT186412T

公开(公告)日：1999-11-15

申请号：AT94303783

申请日：1994-05-25

Applicant: IBM

Inventor： AMINI NADER ,  BLAND PATRICK MAURICE ,  BOURY BECHARA FOUAD ,  HOFMANN RICHARD GERARD ,  LOHMAN TERENCE JOSEPH

IPC: G06F13/28 ,  G06F13/30 ,  G06F13/36 ,  G06F13/40

Abstract: A direct memory access (DMA) support mechanism is provided for use in a computer system 10 which comprises (i) a central processing unit (CPU) 24 connected to system memory 32 by a first system bus 36, and a second system bus 16 connected to the CPU; (ii) a host bridge 20 connecting the second system bus to a peripheral bus 22; (iii) an input/output (I/O) bridge 78 connecting the peripheral bus to a standard I/O bus 92, the standard I/O bus having a plurality of standard I/O devices 90 attached thereto; and (v) arbitration logic 42 which functions in an arbitration mode for arbitrating between the plurality of standard I/O devices competing for access to the standard I/O bus, and in a grant mode wherein a selected standard I/O device is granted access to the standard I/O bus. The DMA support mechanism comprises a direct memory access (DMA) controller 40 for performing DMA cycles on behalf of the selected standard I/O device, and direct memory access (DMA) support logic for enabling the DMA cycles to be performed over the peripheral bus. The DMA support logic includes sideband signals directly connecting the DMA controller with the I/O bridge, the sideband signals including information identifying the bus size of the selected I/O device for which the DMA controller is performing the DMA cycles.

公开(公告)号：CA2080210C

公开(公告)日：1998-10-27

申请号：CA2080210

申请日：1992-10-08

Applicant: IBM

Inventor： LOHMAN TERENCE JOSEPH ,  AMINI NADER ,  BOURY BECHARA FOUAD ,  BRANNON SHERWOOD ,  HORNE RICHARD LOUIS

IPC: G06F13/28 ,  G06F13/16 ,  G06F13/40

Abstract: The present invention provides a bus to bus interface unit for computer systems having dual bus architecture, such as a system bus and an I/O bus. The bus interface unit includes an asynchronous bidirectional temporary data storage function for data being transferred between the two buses to and from devices coupled to each of the two buses. Preferably the storage function operates in modes that will accommodate individual transfers of data, data streaming, and data burst transfers, and can accommodate transfers of information from contiguous addresses without initiating a new request for each address.

公开(公告)号：SG44446A1

公开(公告)日：1997-12-19

申请号：SG1996000483

申请日：1992-12-22

Applicant: IBM

Inventor： AMINI NADER ,  BOURY BECHARA FOUAD ,  SRANNON SHERWOOD ,  HORNE RICHARD LOUIS ,  LOHMAN TERENCE JOSEPH

IPC: G06F13/16 ,  G06F13/28 ,  G06F13/40

Abstract: The present invention provides a bus to bus interface unit for computer systems having dual bus architecture, such as a system bus and an I/O bus. The bus interface unit includes an asynchronous bidirectional temporary data storage function for data being transferred between the two buses to and from devices coupled to each of the two buses. Preferably the storage function operates in modes that will accommodate individual transfers of data, data streaming, and data burst transfers, and can accommodate transfers of information from contiguous addresses without initiating a new request for each address.

公开(公告)号：SG42882A1

公开(公告)日：1997-10-17

申请号：SG1996000412

申请日：1992-12-18

Applicant: IBM

Inventor： AMINI NADER ,  BOURY BECHARA FOUAD ,  HORNE RICHARD LOUIS ,  LOHMAN TERENCE JOSEPH

IPC: G06F13/22 ,  G06F13/36 ,  G06F13/28 ,  G06F13/362 ,  G06F13/20

Abstract: A computer system is provided comprising system memory and a memory controller for controlling access to system memory, a central processing unit electrically connected with the memory controller, and a bus interface unit electrically connected to the memory controller by a system bus and electrically connected to a plurality of input/output devices by an input/output bus. The bus interface unit is able to sense when said one of said input/output devices has completed a read or write operation over said input/output bus, and includes a buffer circuit wherein read and write data transferred between the system bus and the input/output bus via the bus interface unit is temporarily stored during the transfer. Arbitration control logic resides in said bus interface unit and interacts with a central arbitration controller which resides on the system bus. The central arbitration controller responds to the arbitration control logic to simultaneously perform (i) arbitration cycles wherein the central arbitration controller arbitrates between the plurality of input/output devices and the central processing unit to determine which of the input/output devices or the central processing unit should be granted control of the input/output bus and (ii) grant cycles wherein the central arbitration controller grants control of the input/output bus and extends control of the system bus to one of the input/output devices or the central processing unit.

公开(公告)号：CA2080608A1

公开(公告)日：1993-07-03

申请号：CA2080608

申请日：1992-10-15

Applicant: IBM

Inventor： AMINI NADER ,  BOURY BECHARA F ,  BRANNON SHERWOOD ,  HORNE RICHARD L ,  LOHMAN TERENCE J

IPC: G06F13/36 ,  G06F13/16 ,  G06F13/18 ,  G06F13/20

Abstract: BC9-91-089 BUS CONTROL LOGIC FOR COMPUTER SYSTEM HAVING DUAL BUS ARCHITECTURE A computer system is provided, comprising system memory and a memory controller for controlling access to system memory by means of a memory bus, a central processing unit electrically connected with the memory controller for reading and writing data to the system memory over the memory bus, a bus interface unit electrically connected with the memory controller by means of a system bus, and an input/output device electrically connected to the bus interface unit by an input/output bus. The memory controller incorporates logic for arbitrating between the central processing unit and the input/output device to determine which of the central processing unit and the input/output device should be granted access to the system memory through said memory bus. The bus interface unit incorporates logic for overriding the memory controller logic, in response to a series of predetermined operating conditions, and grant exclusive access to system memory to the input/output device.