公开(公告)号：CA2055783A1

公开(公告)日：1992-05-16

申请号：CA2055783

申请日：1991-10-22

Applicant: IBM

Inventor： JOHNSON LEE E JR ,  KOKOSZKA DARYL J

IPC: G09G5/20 ,  G06T11/20 ,  G06T15/83 ,  G06T15/87

Abstract: AT9-90-055 A bitblt and line draw parameter calculator for preprocessing address information for a bitblt and line draw sequencer. The sequencer computes individual pixel addresses, controls color interpolation pacing and communicates with the memory hypervisor. By partitioning memory addressing into two tasks a first line or bitblt need only be partially processed prior to starting processing on a second line or bitblt.

公开(公告)号：CA2055784C

公开(公告)日：1998-05-19

申请号：CA2055784

申请日：1991-10-22

Applicant: IBM

Inventor： KOKOSZKA DARYL J ,  LARKY STEVEN P ,  JOHNSON LEE E JR

IPC: G06F12/08 ,  G06T15/00

Abstract: A memory apparatus including a circuit for receiving and serially storing a plurality of instructions and a plurality of buffer memories each including a buffer controller for regulating access to that buffer. Also included is a circuit, connected to each buffer controller and said receiving circuit, for accessing one or more of said buffers in response to at least one other serially stored instruction, accessing at least one remaining buffer.

公开(公告)号：CA2055784A1

公开(公告)日：1992-05-16

申请号：CA2055784

申请日：1991-10-22

Applicant: IBM

Inventor： JOHNSON LEE E JR ,  KOKOSZKA DARYL J ,  LARKY STEVEN P

IPC: G06F12/08 ,  G06T15/00

Abstract: A memory system including a circuit for receiving and serially storing a plurality of instructions and a plurality of buffer memories each including a buffer controller 800, 820 for regulating access to that buffer. Also included is a circuit 830, connected to each buffer controller and said receiving circuit, for accessing one or more of said buffers in response to a first serially stored instruction while, in response to at least one other serially stored instruction, accessing at least one remaining buffer.

公开(公告)号：CA2055785A1

公开(公告)日：1992-05-16

申请号：CA2055785

申请日：1991-10-22

Applicant: IBM

Inventor： JOHNSON LEE E JR ,  KOKOSZKA DARYL J ,  LARKY STEVEN P ,  SIDOLI PAOLO

IPC: G06F3/153 ,  G06T11/20 ,  G06T15/83 ,  G06T15/87

Abstract: AT9-89-107 A graphics processor including an interface for providing triangle primitives and line primitives representing a graphical image, a line drawer for receiving line primitives and for rendering the line primitives, and a triangle interpolator for receiving the triangle primitives from the interface and for providing line primitives therefrom to the line drawer, wherein the interface includes a register for storing graphics image line primitives and for selectively providing the stored line primitives to the line drawer.

公开(公告)号：CA2053947A1

公开(公告)日：1992-05-16

申请号：CA2053947

申请日：1991-10-22

Applicant: IBM

Inventor： JOHNSON LEE E JR ,  KOKOSZKA DARYL J ,  LARKY STEVEN P ,  SIDOLI PAOLO

IPC: G06F3/153 ,  G06T11/20 ,  G06T15/00 ,  G06T15/80 ,  G06F15/66

Abstract: r9-90-022 A graphics processor including an interface for providing triangle primitives representing a graphics image, a triangle interpolator coupled to the interface for interpolating a triangle primitive and serially computing multiple line primitives from the triangle primitive, a line renderer coupled to the triangle interpolator for receiving a line primitive from the triangle interpolator and for providing pixels representing the line primitive while the triangle interpolator is computing another line primitive.