Dynamic two device memory cell which provides D.C. sense signals
    1.
    发明授权
    Dynamic two device memory cell which provides D.C. sense signals 失效
    提供直流感测信号的动态双器件存储单元

    公开(公告)号:US3919569A

    公开(公告)日:1975-11-11

    申请号:US31940272

    申请日:1972-12-29

    Applicant: IBM

    Abstract: A semiconductor two device memory cell is disclosed in which the two devices are complementary. The cell is best implemented in the integrated circuit environment and may be fabricated using well known non-complementary fabrication techniques. The cell incorporates a floating region or substrate - within - a substrate on which charge is stored in different amounts to achieve different potentials on the region thereby controlling, in one mode, the threshold of a field effect transistor of which the floating region forms a part. In a different mode, the floating region or substrate forms a drain or source region for a switching transistor which is formed in its own substrate. The latter substrate, which is formed from a semiconductor chip or wafer, besides forming the channel region of the switching transistor acts as a source for a sensing transistor which is formed by a region of opposite conductivity type in the floating region, the floating region and the substrate itself. The floating region is charged to one of two potentials when the floating region is a drain or source of the switching transistor and, the amount of current flow is controlled by the potential on the floating region when it operates as the substrate for the sensing transistor.

    Abstract translation: 公开了半导体二器件存储单元,其中两个器件是互补的。 该电池最好在集成电路环境中实现,并且可以使用公知的非互补制造技术来制造。 电池结合了浮动区域或衬底,其中以不同的量存储电荷,以在该区域上实现不同的电位,从而在一种模式中控制浮动区域形成的场效应晶体管的阈值 部分。 在不同的模式中,浮动区域或衬底形成用于其自身衬底中形成的开关晶体管的漏极或源极区域。 除了形成开关晶体管的沟道区域之外,由半导体芯片或晶片形成的后一基板用作感测晶体管的源极,该感测晶体管由浮动区域中的相反导电类型的区域,浮动区域和 底物本身。 当浮动区域是开关晶体管的漏极或源极时,浮置区域被充电到两个电位之一,并且当其作为感测晶体管的衬底操作时,电流的流量由浮置区域上的电位来控制。

    DYNAMIC TWO DEVICE MEMORY CELL WHICH PROVIDES D.C. SENSE SIGNALS

    公开(公告)号:CA998769A

    公开(公告)日:1976-10-19

    申请号:CA186206

    申请日:1973-11-20

    Applicant: IBM

    Abstract: A semiconductor two device memory cell is disclosed in which the two devices are complementary. The cell is best implemented in the integrated circuit environment and may be fabricated using well known non-complementary fabrication techniques. The cell incorporates a floating region or substrate - within - a - substrate on which charge is stored in different amounts to achieve different potentials on the region thereby controlling, in one mode, the threshold of a field effect transistor of which the floating region forms a part. In a different mode, the floating region or substrate forms a drain or source region for a switching transistor which is formed in its own substrate. The latter substrate, which is formed from a semiconductor chip or wafer, besides forming the channel region of the switching transistor acts as a source for a sensing transistor which is formed by a region of opposite conductivity type in the floating region, the floating region and the substrate itself. The floating region is charged to one of two potentials when the floating region is a drain or source of the switching transistor and, the amount of current flow is controlled by the potential on the floating region when it operates as the substrate for the sensing transistor.

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