公开(公告)号：US3573505A

公开(公告)日：1971-04-06

申请号：US3573505D

申请日：1968-07-15

Applicant: IBM

Inventor： GAENSSLEN FRITZ H ,  SPAMPINATO DOMINIC P

IPC: G11C11/412 ,  H03K3/356 ,  H03K3/26

CPC classification number: H03K3/35606 ,  G11C11/412

Abstract: A memory cell in which the load devices thereof are unidirectional devices such as diodes, In the cell, where the storage devices are PNP or NPN devices, the diode load devices are disposed in the circuit such that the PN junctions of the diodes are backward biased. The storage devices, which are crosscoupled, and the diode load devices are connected at nodes to which gated drivers are also connected for the purpose of applying appropriate voltages to the nodes and, therefore, to the gate electrodes of the storage devices to change the conducting state of the storage devices during an active state. The gated drivers when turned on, also provide a portion of a current path to detect the conducting state of one or the other of the storage devices. In a quiescent state, the diode load devices in conjunction with a backward-biased PN junction portion of the OFF storage device form a nonlinear voltage divider which, because of their relative impedances, apply a voltage at the node of the OFF storage device to which the gate of the ON storage device is connected which maintains that storage device in the ON condition during the quiescent state. A bistable circuit and a nondestructive readout memory array are also disclosed.

公开(公告)号：US3560940A

公开(公告)日：1971-02-02

申请号：US3560940D

申请日：1968-07-15

Applicant: IBM

Inventor： GAENSSLEN FRITZ H

IPC: G11C11/41 ,  G11C8/00 ,  G11C8/16 ,  G11C11/408 ,  G11C11/412 ,  G11C11/418 ,  G11C11/40 ,  H03K3/286

CPC classification number: G11C11/4087 ,  G11C8/00 ,  G11C8/16 ,  G11C11/412 ,  G11C11/418

Abstract: AN ARRAY OF ACTUABLE DEVICES EACH REQUIRING TWO INPUTS FOR ACTUATING IS DISCLOSED. DURING A FIRST TIME PERIOD, ONE ROW OF THE ARRAY IS SEPARATELY ACTUABLE VIA COMMON INTERCONNECTIONS TO COLUMNS OF ACTUABLE DEVICES AND A COMMON ROW CONNECTION AND STORES INFORMATION IN BINARY FORM. EACH OF THE DEVICES IN THE ROW IS CONNECTED TO A COLUMN F ACTUABLE DEVICES AND TO AN ACTUABLE GATE WHICH IS ACTUATED OR NOT ACTUATED DEPENDING ON THE STATE OF THE ACTUABLE DEVICES OF THE SEPARATELY CTUATED ROW. EACH GATE IS ALSO CONNECTED TO S SEPARATE ROW OF THE ARRAY. DURING A SECOND TIME PERIOD, THE COLUMNS OF ACTUABLE DEVICES, ARE ACTUATED FROM PULSED SOURCES VIA THEIR COMMON INTERCONNECTION AND FROM IS PULSED SOURCE CONNECTED IN COMMON TO ALL THE GATES. SINCE ONLY ONE GATE CONNECTED TO A ROW IS ACTUATED AND ALL COLUMNS OF DEVICES ARE ACTUATED, ONLY THOSE DEVICES IN THAT ROW ARE ACTUATED. IN A MEMORY ENVIRONMENT, THE FOREGOING OPERATION IS CHARACTERIZED AS WRITING. TO DETECT THE CONDITION OF SELECTED OF THE ACTUATED DEVICES, AN ACTUABLE GATE IS SELECTED DURING A FIRST TIME PERIOD AND, DURING A SECOND TIME PERIOD, SENSING DEVICES ARE CONNECTED TO THE COLUMNS OF ACTUABLE DE-
VICES AND, THE COMMON INTERCONNECTION TO A ROW OF ACTUABLE DEVICES IS ACTIVATED FROM A PULSED SOURCE. IN A MEMORY INVIRONMENT, THE FOREGOING OPERATION IS CHARACTERIZED AS READING. THE ACTUABLE DEVICES MAY BE MEMORY CELLS, BISTABLE CIRCUITS OR THE LIKE. THE ARRANGEMENT SHOWN IS PARTICULARLY ADAPTED TO THE SEMICONDUCTOR CHIP ENVIRONMENT WHERE REDUCTION OF INTERCONNECTIONS IS A SIGNIFICANT DESIGN FACTOR. OTHER ARRANGEMENTS SHOWING DECODING ON THE CHIP AND MORE THAN TWO TIME PERIODS ARE ALSO DIS CLOSED.

公开(公告)号：US3919569A

公开(公告)日：1975-11-11

申请号：US31940272

申请日：1972-12-29

Applicant: IBM

Inventor： GAENSSLEN FRITZ H ,  KRICK PAUL J

IPC: G11C11/405 ,  G11C11/403 ,  G11C11/404 ,  H01L21/8242 ,  H01L27/092 ,  H01L27/108 ,  H03K3/26 ,  H03K19/08

CPC classification number: H01L29/7841 ,  G11C11/403 ,  G11C11/404 ,  H01L27/092 ,  H01L27/108

Abstract: A semiconductor two device memory cell is disclosed in which the two devices are complementary. The cell is best implemented in the integrated circuit environment and may be fabricated using well known non-complementary fabrication techniques. The cell incorporates a floating region or substrate - within - a substrate on which charge is stored in different amounts to achieve different potentials on the region thereby controlling, in one mode, the threshold of a field effect transistor of which the floating region forms a part. In a different mode, the floating region or substrate forms a drain or source region for a switching transistor which is formed in its own substrate. The latter substrate, which is formed from a semiconductor chip or wafer, besides forming the channel region of the switching transistor acts as a source for a sensing transistor which is formed by a region of opposite conductivity type in the floating region, the floating region and the substrate itself. The floating region is charged to one of two potentials when the floating region is a drain or source of the switching transistor and, the amount of current flow is controlled by the potential on the floating region when it operates as the substrate for the sensing transistor.

Abstract translation: 公开了半导体二器件存储单元，其中两个器件是互补的。 该电池最好在集成电路环境中实现，并且可以使用公知的非互补制造技术来制造。 电池结合了浮动区域或衬底，其中以不同的量存储电荷，以在该区域上实现不同的电位，从而在一种模式中控制浮动区域形成的场效应晶体管的阈值 部分。 在不同的模式中，浮动区域或衬底形成用于其自身衬底中形成的开关晶体管的漏极或源极区域。 除了形成开关晶体管的沟道区域之外，由半导体芯片或晶片形成的后一基板用作感测晶体管的源极，该感测晶体管由浮动区域中的相反导电类型的区域，浮动区域和 底物本身。 当浮动区域是开关晶体管的漏极或源极时，浮置区域被充电到两个电位之一，并且当其作为感测晶体管的衬底操作时，电流的流量由浮置区域上的电位来控制。

公开(公告)号：US3535699A

公开(公告)日：1970-10-20

申请号：US3535699D

申请日：1968-01-15

Applicant: IBM

Inventor： GAENSSLEN FRITZ H ,  SPAMPINATO DOMINIC P

IPC: G11C11/402 ,  G11C7/00 ,  G11C11/40

CPC classification number: G11C11/4023

公开(公告)号：CA1130473A

公开(公告)日：1982-08-24

申请号：CA337644

申请日：1979-10-15

Applicant: IBM

Inventor： CROWDER BILLY L ,  GAENSSLEN FRITZ H ,  JAEGER RICHARD C

IPC: H01L29/78 ,  H01L21/265 ,  H01L29/10 ,  H01L29/167

Abstract: MOSFET SUBSTRATE SENSITIVITY CONTROL The sensitivity of the threshold voltage in MOSFET devices to changes in substrate voltage may be reduced at a given temperature by the introduction of sufficiently deep energy level, low diffusivity impurities into the depletion region under the gate of the MOSFET. Y0978-020

公开(公告)号：CA915305A

公开(公告)日：1972-11-21

申请号：CA915305D

Applicant: IBM

Inventor： GAENSSLEN FRITZ H

IPC: G11C8/00 ,  G11C8/16 ,  G11C11/40 ,  G11C11/408 ,  G11C11/412 ,  G11C11/418 ,  H03K3/286

公开(公告)号：IT1151056B

公开(公告)日：1986-12-17

申请号：IT2041280

申请日：1980-03-07

Applicant: IBM

Inventor： GAENSSLEN FRITZ H ,  SPILLER EBERHARD A

IPC: H01L29/80 ,  H01L21/027 ,  H01L21/033 ,  H01L21/3205 ,  H01L21/338 ,  H01L29/78 ,  H01L29/812 ,  H01L

Abstract: A method is disclosed for fabricating structures having electrically conductive regions such as high resolution semiconductor device and circuit designs which require only low resolution alignment steps during fabrication. The method is used to fabricate metal semiconductor field effect transistors (MESFET) and metal oxide semiconductor field effect transistors (MOSFET) devices and incorporates the following features. A device with very small (i.e. submicron) dimensions is positioned in a relatively large device well such that the exact position of the device in its well is not critical. Isolation and interconnection of devices in different wells is achieved by standard masking and alignment techniques with a resolution corresponding to the larger dimensions of the device wells. All high resolution features of the device are contained in a single masking level, however, to separate and insulate different elements of the device at such small dimensions different height levels are used in the device so that one masking step can produce zero lateral spacing between the different device elements. The disclosure provides examples of the present method applied to the fabrication of a MESFET device and a MOSFET device and to the isolation and interconnection of single devices into large circuits on a semiconductor chip.

公开(公告)号：CA1126876A

公开(公告)日：1982-06-29

申请号：CA345149

申请日：1980-02-06

Applicant: IBM

Inventor： GAENSSLEN FRITZ H ,  SPILLER EBERHARD A

IPC: H01L29/80 ,  H01L21/027 ,  H01L21/033 ,  H01L21/3205 ,  H01L21/338 ,  H01L29/78 ,  H01L29/812 ,  H01L21/302

Abstract: METHOD FOR FABRICATING SELF-ALIGNED HIGH RESOLUTION NON PLANAR DEVICES EMPLOYING LOW RESOLUTION REGISTRATION A method is disclosed for fabricating structures having electrically conductive regions such as high resolution semiconductor device and circuit designs which require only low resolution alignment steps during fabrication. The method is used to fabricate metal semiconductor field effect transistors(MESFET) and metal oxide semiconductor field effect transistors (MOSFET) devices and incorporates the following features. A device with very small (i.e. submicron) dimensions is positioned in a relatively large device well such that the exact position of the device in its well is not critical. Isolation and interconnection of devices in different wells is achieved by standard masking and alignment techniques with a resolution corresponding to the larger dimensions of the device wells. All high resolution features of the device are contained in a single masking level, however, to separate and insulate different elements of the device at such small dimensions different height levels are used in the device so that one masking step can produce zero lateral spacing between the different device YO978-012 elements. The disclosure provides examples of the present method applied to the fabrication of a MESFET device and a MOSFET device and to the isolation and interconnection of single devices into large circuits on a semiconductor chip. YO978-012

公开(公告)号：CA1092726A

公开(公告)日：1980-12-30

申请号：CA308257

申请日：1978-07-27

Applicant: IBM

Inventor： GAENSSLEN FRITZ H

IPC: H01L29/78 ,  H01L21/28 ,  H01L21/321 ,  H01L21/336 ,  H01L21/768 ,  H01L23/532 ,  H01L29/423 ,  H01L29/43 ,  H01L29/49 ,  H01L21/76 ,  B05D5/12

Abstract: STRUCTURE AND FABRICATION METHOD FOR INTEGRATED CIRCUITS WITH POLYSILICON LINES HAVING LOW SHEET RESISTANCE A method and structure for polysilicon lines which include a silicide layer for providing a low sheet resistance. The invention may be employed in a polysilicon gate MOSFET process for integrated circuits as well as other integrated structures. In the method a first layer of polysilicon is deposited followed by a deposition of a metal of the silicide forming type. Another polysilicon layer is then deposited on top of the silicide forming metal to produce a three layer structure. The three layer structure is subjected to heat, for example, during the reoxidation step in a gate fabrication process, the metal reacts with the polysilicon at two reaction fronts to form a silicide. The resultant silicide has a much lower resistivity than doped polysilicon and therefore provides a second conductive layer which can be used more compatibly and efficiently in connection with the normal metal layer employed in integrated circuits to give a two-dimensional degree of freedom for the distribution of signals.

公开(公告)号：IT8020412D0

公开(公告)日：1980-03-07

申请号：IT2041280

申请日：1980-03-07

Applicant: IBM

Inventor： GAENSSLEN FRITZ H ,  SPILLER EBERHARD A

IPC: H01L29/80 ,  H01L21/027 ,  H01L21/033 ,  H01L21/3205 ,  H01L21/338 ,  H01L29/78 ,  H01L29/812 ,  H01L

Abstract: A method is disclosed for fabricating structures having electrically conductive regions such as high resolution semiconductor device and circuit designs which require only low resolution alignment steps during fabrication. The method is used to fabricate metal semiconductor field effect transistors (MESFET) and metal oxide semiconductor field effect transistors (MOSFET) devices and incorporates the following features. A device with very small (i.e. submicron) dimensions is positioned in a relatively large device well such that the exact position of the device in its well is not critical. Isolation and interconnection of devices in different wells is achieved by standard masking and alignment techniques with a resolution corresponding to the larger dimensions of the device wells. All high resolution features of the device are contained in a single masking level, however, to separate and insulate different elements of the device at such small dimensions different height levels are used in the device so that one masking step can produce zero lateral spacing between the different device elements. The disclosure provides examples of the present method applied to the fabrication of a MESFET device and a MOSFET device and to the isolation and interconnection of single devices into large circuits on a semiconductor chip.