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公开(公告)号：US3453600A
公开(公告)日：1969-07-01
申请号：US3453600D
申请日：1966-08-18
Applicant: IBM
Inventor： STAFFORD THOMAS S , KRYGOWSKI MATTHEW A
CPC classification number: G06F9/4843 , G06F13/26
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公开(公告)号：US3399384A
公开(公告)日：1968-08-27
申请号：US48632665
申请日：1965-09-10
Applicant: IBM
Inventor： CROCKETT PETER N , KRYGOWSKI MATTHEW A , STAFFORD THOMAS S
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公开(公告)号：CA1224572A
公开(公告)日：1987-07-21
申请号：CA478629
申请日：1985-04-09
Applicant: IBM
Abstract: A fast path (comprising control and data busses) directly connects between a storage element in a storage hierarchy and a requestor. The fast path (FP) is in parallel with the bus path normally provided through the storage hierarchy between the requestor and the storage element controller. The fast path may bypass intermediate levels in the storage hierarchy. The fast path is used at least for fetch requests from the requestor, since fetch requests have been found to comprise the majority of all storage access requests. System efficiency is significantly increased by using at least one fast path in a system to decrease the peak loads on the normal path. A requestor using the fast path make each fetch request simultaneously to the fast path and to the normal path in a system controller element (SCE). The request through the fast path gets to the storage element before the same request through the SCE, but may be ignored by the storage element if it is busy. If accepted, the storage element can start its accessing controls sooner for a fast path request, than if the request is received from the normal path. Every request must use SCE controlled cross-interrogate (XI) and storage protect (SP) resources. Fast path request operation requires unique coordination among the XI and SP controls, the SCE priority controls, and by the storage element priority controls. When the accessed data is ready to be sent by the storage element, it can be sent to the requestor faster on the fast path data bus than on the SCE data bus. The fast path data bus may be used to transfer data for requests ignored from the fast path.
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公开(公告)号：CA2056716A1
公开(公告)日：1992-07-17
申请号：CA2056716
申请日：1991-11-29
Applicant: IBM
Inventor： BEAN BRADFORD M , BIERCE ANNE E , CHRISTENSEN NEAL T , CLARK LEO J , JONES CHRISTINE C , KRYGOWSKI MATTHEW A , REICK KEVIN F
Abstract: PO9-90-010 Plural requests for storage accessing are processed in plural stages of a storage-request pipeline. Pipeline processing is not interrupted when one or more requests must wait for a resource to start its processing, or when a pipeline stage must process for a long period in relation to the time allocated for a processing operation in the pipeline. Waiting is done in a wait path connected to a particular processing stage in the pipeline. A request is shunted from the pipeline into a wait path when processing the request in the pipeline would delay pipeline processing. When the wait has ended, a request re-enters the pipeline from its wait path. The pipeline is provided in a multiprocessor (MP) in which storage requests are provided asynchronously to a tightly coupled system storage and usually may be handled and processed asynchronously by the pipeline. The pipeline output may direct the processed requests to a shared intermediate cache or to the system main storage.
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Patent Agency Ranking
公开(公告)号：CA1103324A
公开(公告)日：1981-06-16
申请号：CA301828
申请日：1978-04-24
Applicant: IBM
Inventor： CAPOWSKI ROBERT S , KRYGOWSKI MATTHEW A , ZIMMERMAN TERRENCE K
Abstract: REQUEST FORWARDING SYSTEM Storage access requests are forwarded from plural input/output channels to shared main storage. An address word in each request designates the identity of the source channel (CHID) and "destination" address (of a doubleword space in storage relative to which one, two or four "data" words shall be transferred). EOT tag signal provides demarcation of requests and also uniquely identifies "l-wide" input (Store) requests. Quadword (QW) tag, presented with "4-wide" requests, enables the storage access system to use a single address in the request to locate two contiguous doubleword spaces in storage. Data tags (Dl, D2), presented on a selective basis enable the access system to selectively steer (reorder the positions of) data words in an input request relative to word halves of the addressed space. Consequently the data repositioning function associated with Read Backward operations does not require reordering of data words in the channel buffers (saving handling time and expense of "steering" circuits in the individual channels). In association with a "l-wide" input request a single data tag, Dl or D2, is used to steer the single data word of the request into either half of the addressed space on a selective basis.
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公开(公告)号：CA1102005A
公开(公告)日：1981-05-26
申请号：CA301763
申请日：1978-04-24
Applicant: IBM
Inventor： KRYGOWSKI MATTHEW A
Abstract: CHANNEL STORAGE ADAPTER This adapter operates in time division multiplex mode between an input/output channel processing subsystem and a storage access subsystem of a data processing system. The adapter is capable of sustaining multiple processes of information transfer concurrently relative to both subsystems. It is also capable of concurrently sustaining ancillary processes for verifying and timing out individual transactions of the information transfer processes.
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公开(公告)号：CA791883A
公开(公告)日：1968-08-06
申请号：CA791883D
Applicant: IBM
Inventor： STAFFORD THOMAS S , KRYGOWSKI MATTHEW A , CROCKETT PETER N
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公开(公告)号：FR2397015A1
公开(公告)日：1979-02-02
申请号：FR7818485
申请日：1978-06-13
Applicant: IBM
Inventor： CAPOWSKI ROBERT S , KRYGOWSKI MATTHEW A , ZIMMERMAN TERRENCE K
Abstract: Storage access requests are forwarded from plural input/output channels to shared main storage. An address word in each request designates the identity of the source channel (CHID) and "destination" address (of a doubleword space in storage relative to which one, two or four "data" words shall be transferred). EOT tag signal provides demarcation of requests and also uniquely identifies "1-wide" input (Store) requests. Quadword (QW) tag, presented with "4-wide" requests, enables the storage access system to use a single address in the request to locate two contiguous doubleword spaces in storage. Data tags (D1, D2), presented on a selective basis enable the access system to selectively steer (reorder the positions of) data words in an input request relative to word halves of the addressed space. Consequently the data repositioning function associated with Read Backward operations does not require reordering of data words in the channel buffers (saving handling time and expense of "steering" circuits in the individual channels). In association with a "1-wide" input request a single data tag, D1 or D2, is used to steer the single data word of the request into either half of the addressed space on a selective basis.
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公开(公告)号：FR2397014A1
公开(公告)日：1979-02-02
申请号：FR7817692
申请日：1978-06-05
Applicant: IBM
Inventor： KRYGOWSKI MATTHEW A
Abstract: This adapter operates in time division multiplex mode between an input/output channel processing subsystem and a storage access subsystem of a data processing system. The adapter is capable of sustaining multiple processes of information transfer concurrently relative to both subsystems. It is also capable of concurrently sustaining ancillary processes for verifying and timing out individual transactions of the information transfer processes.
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