公开(公告)号：DE3585970D1

公开(公告)日：1992-06-11

申请号：DE3585970

申请日：1985-06-19

Applicant: IBM

Inventor： CHIESA GEORGE LOUIS ,  KRYGOWSKI MATTHEW ANTHONY ,  MESSINA BENEDICTO UMBERTO ,  PAPANASTASIOU THEODORE ATHANAS

IPC: G06F15/16 ,  G06F12/08 ,  G06F13/16 ,  G06F13/18

Abstract: A fast path (comprising control and data busses) directly connects between a storage controller (18) in a main storage (21) and a requestor (CPU). The fast path (12) is in parallel with the bus path (11, 16, 14) normally provided through the storage hierarchy between the requestor (CPU) and the storage controller (18). The fast path (12) may bypass intermediate levels in the storage hierarchy. The fast path (12) is used at least for fetch requests from the requestor (CPU), since fetch request have been found to comprise the majority of all storage access requests. System efficiency is significantly increased by using at least one fast path (12) in a system to decrease the peak loads on the normal path (11, 16, 14). A requestor (CPU) using the fast path (12) and to the normal path (11, 16, 14) in a system controller element (16). The request through the fast path (12) gets to the main storage (21) before the same request gets through the system controller element, but may be ignored by the storage (21) if the latter is busy. If accepted, the storage (21) can start its accessing controls sooner for a fast path request than if the request is received from the normal path. Every request must use controlled cross-interrogate (17) and storage protect (19) resources. Fast path request SP controls, the SCE priority controls, and by the storage element priority controls. When the accessed data is ready to be sent by the main storage (21), it can be sent to the requestor (CPU) faster on the fast path data bus (12) than on the SCE data bus (11,16,14). The fast path data bus (12) may be used to transfer data for requests ignored from the fast path.

公开(公告)号：DE3380533D1

公开(公告)日：1989-10-12

申请号：DE3380533

申请日：1983-05-06

Applicant: IBM

Inventor： KRYGOWSKI MATTHEW ANTHONY ,  MESSINA BENEDICTO UMBERTO ,  SILKMAN WILLIAM DEAN

IPC: G06F15/16 ,  G06F12/08 ,  G06F12/16

Abstract: In a data processing system having multiple processors with individual cache stores, a cross-interrogation is made in other caches if requested data is not found in the local associated cache. Data paths (67, 74, 83, 86, 201, 202, 203, 207,208) and communication controls (20, 21, 22, 23, 50, 76, 77) are provided to enable direct cache-to-cache and cache-to-channel data transfers thus saving main storage accesses and the necessity to wait for main storage availability.

公开(公告)号：DE2828731A1

公开(公告)日：1979-01-25

申请号：DE2828731

申请日：1978-06-30

Applicant: IBM

Inventor： KRYGOWSKI MATTHEW ANTHONY

IPC: G06F13/42 ,  G06F13/12 ,  G06F9/18 ,  G06F3/00 ,  G11C9/00

Abstract: This adapter operates in time division multiplex mode between an input/output channel processing subsystem and a storage access subsystem of a data processing system. The adapter is capable of sustaining multiple processes of information transfer concurrently relative to both subsystems. It is also capable of concurrently sustaining ancillary processes for verifying and timing out individual transactions of the information transfer processes.

公开(公告)号：CH634671A5

公开(公告)日：1983-02-15

申请号：CH652678

申请日：1978-06-15

Applicant: IBM

Inventor： KRYGOWSKI MATTHEW ANTHONY

IPC: G06F13/42 ,  G06F13/12 ,  G06F3/04 ,  G06F13/00

公开(公告)号：DE2828741A1

公开(公告)日：1979-01-25

申请号：DE2828741

申请日：1978-06-30

Applicant: IBM

Inventor： CAPOWSKI ROBERT STANLEY ,  KRYGOWSKI MATTHEW ANTHONY ,  ZIMMERMANN TERRENCE KEITH

IPC: G06F13/28 ,  G06F12/04 ,  G06F13/12 ,  G06F13/18 ,  G06F9/18 ,  G06F3/00 ,  G11C9/00

Abstract: Storage access requests are forwarded from plural input/output channels to shared main storage. An address word in each request designates the identity of the source channel (CHID) and "destination" address (of a doubleword space in storage relative to which one, two or four "data" words shall be transferred). EOT tag signal provides demarcation of requests and also uniquely identifies "1-wide" input (Store) requests. Quadword (QW) tag, presented with "4-wide" requests, enables the storage access system to use a single address in the request to locate two contiguous doubleword spaces in storage. Data tags (D1, D2), presented on a selective basis enable the access system to selectively steer (reorder the positions of) data words in an input request relative to word halves of the addressed space. Consequently the data repositioning function associated with Read Backward operations does not require reordering of data words in the channel buffers (saving handling time and expense of "steering" circuits in the individual channels). In association with a "1-wide" input request a single data tag, D1 or D2, is used to steer the single data word of the request into either half of the addressed space on a selective basis.

公开(公告)号：CH634938A5

公开(公告)日：1983-02-28

申请号：CH674678

申请日：1978-06-21

Applicant: IBM

Inventor： CAPOWSKI ROBERT STANLEY ,  KRYGOWSKI MATTHEW ANTHONY ,  ZIMMERMANN TERRENCE KEITH

IPC: G06F13/28 ,  G06F12/04 ,  G06F13/12 ,  G06F13/18 ,  G06F13/00

公开(公告)号：AU3630578A

公开(公告)日：1979-11-22

申请号：AU3630578

申请日：1978-05-19

Applicant: IBM

Inventor： CAPOWSKI ROBERT STANLEY ,  KRYGOWSKI MATTHEW ANTHONY ,  ZIMMERMAN TERRANCE KEITH

IPC: G06F13/28 ,  G06F12/04 ,  G06F13/12 ,  G06F13/18 ,  G06F3/00 ,  G06F9/18 ,  G06F13/00

Abstract: Storage access requests are forwarded from plural input/output channels to shared main storage. An address word in each request designates the identity of the source channel (CHID) and "destination" address (of a doubleword space in storage relative to which one, two or four "data" words shall be transferred). EOT tag signal provides demarcation of requests and also uniquely identifies "1-wide" input (Store) requests. Quadword (QW) tag, presented with "4-wide" requests, enables the storage access system to use a single address in the request to locate two contiguous doubleword spaces in storage. Data tags (D1, D2), presented on a selective basis enable the access system to selectively steer (reorder the positions of) data words in an input request relative to word halves of the addressed space. Consequently the data repositioning function associated with Read Backward operations does not require reordering of data words in the channel buffers (saving handling time and expense of "steering" circuits in the individual channels). In association with a "1-wide" input request a single data tag, D1 or D2, is used to steer the single data word of the request into either half of the addressed space on a selective basis.

公开(公告)号：AU3630478A

公开(公告)日：1979-11-22

申请号：AU3630478

申请日：1978-05-16

Applicant: IBM

Inventor： KRYGOWSKI MATTHEW ANTHONY

IPC: G06F13/42 ,  G06F13/12 ,  G06F3/00 ,  G06F9/18 ,  G06F13/00

Abstract: This adapter operates in time division multiplex mode between an input/output channel processing subsystem and a storage access subsystem of a data processing system. The adapter is capable of sustaining multiple processes of information transfer concurrently relative to both subsystems. It is also capable of concurrently sustaining ancillary processes for verifying and timing out individual transactions of the information transfer processes.