公开(公告)号：DE69332558D1

公开(公告)日：2003-01-23

申请号：DE69332558

申请日：1993-10-05

Applicant: IBM

Inventor： CHANG PAUL ,  KU EDWARD HAU-CHUN ,  COATES JOSEPH WAYNE ,  SANAYE SIMIN HOSNE

IPC: H04L12/46

Abstract: A multiport bridge includes a plurality of Bridge Port Frame Handler (BPFH) units (1'',2'',...N'') coupled through a Source Routing bus and a Transparent Bridge Bus to a microcontroller (20), a Packet Memory (12) and a Transparent Bridge Control Management System (TBCMS) (26). Each Bridge Port Frame Handler unit receives Frame from its attached LAN, forwards selected portions of Source Routing Frames to other Bridge Port Frame Handlers for further processing. Likewise, selected portions of Transparent Bridge Frames are forwarded to the TBCMS whereat routing information and signature information is extracted and returned to the forwarding BPFH unit for further processing.

公开(公告)号：DE69332558T2

公开(公告)日：2003-09-25

申请号：DE69332558

申请日：1993-10-05

Applicant: IBM

Inventor： CHANG PAUL ,  KU EDWARD HAU-CHUN ,  COATES JOSEPH WAYNE ,  SANAYE SIMIN HOSNE

IPC: H04L12/46

Abstract: A multiport bridge includes a plurality of Bridge Port Frame Handler (BPFH) units (1'',2'',...N'') coupled through a Source Routing bus and a Transparent Bridge Bus to a microcontroller (20), a Packet Memory (12) and a Transparent Bridge Control Management System (TBCMS) (26). Each Bridge Port Frame Handler unit receives Frame from its attached LAN, forwards selected portions of Source Routing Frames to other Bridge Port Frame Handlers for further processing. Likewise, selected portions of Transparent Bridge Frames are forwarded to the TBCMS whereat routing information and signature information is extracted and returned to the forwarding BPFH unit for further processing.

公开(公告)号：DE3172748D1

公开(公告)日：1985-12-05

申请号：DE3172748

申请日：1981-05-12

Applicant: IBM

Inventor： KU EDWARD HAU-CHUN ,  ROHRER GENE DALE

IPC: G06K7/08 ,  G06K9/00 ,  G06K9/20 ,  G06K9/70 ,  G06K9/18

Abstract: A character recognition system including a timing subsystem, comprising a base oscillator or clock (13) and adaptive timing circuits (39) driven by the base clock to provide a plurality of timing pulses for timing the operation of the entire system. The timing circuits are governed in part by delay circuits which are in turn controlled by the amplitude and location of peak signals derived from scanning earlier pulses.