公开(公告)号：JP2010272859A

公开(公告)日：2010-12-02

申请号：JP2010108180

申请日：2010-05-10

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHANG JOSEPHINE B ,  GUILLORN MICHAEL A ,  SLEIGHT JEFFREY W ,  CHANG PAUL

IPC: H01L29/786 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092

CPC classification number: H01L27/1203 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78696 ,  Y10S977/762 ,  Y10S977/938

Abstract: PROBLEM TO BE SOLVED: To provide a nanowire mesh of a single gate inverter and a method of fabricating the same. SOLUTION: The field effect transistor (FET) includes a plurality of device layers disposed vertically in a stack, each device layer has a source region, a drain region and a plurality of nanowire channels 110 connecting the source region and the drain region, wherein the source and drain regions of one or more of the device layers are doped with an n-type dopant or a p-type dopant. The FET inverter further includes a common gate 150 surrounding the plurality of nanowire channels, a first contact 156 to the source regions of the one or more device layers doped with the n-type dopant, a second contact 158 to the source regions of the one or more device layers doped with the p-type dopant, and a common third contact 152 to the drain regions of each of the device layers. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供单栅极逆变器的纳米线网及其制造方法。 解决方案：场效应晶体管（FET）包括在堆叠中垂直设置的多个器件层，每个器件层具有源极区，漏极区和连接源极区和漏极区的多个纳米线通道110 其中一个或多个器件层的源区和漏区掺杂有n型掺杂剂或p型掺杂剂。 FET反相器还包括围绕多个纳米线通道的公共栅极150，向掺杂有n型掺杂剂的一个或多个器件层的源极区域提供的第一接触156，一个或多个纳米线通道的源极区域的第二接触158 或更多的掺杂有p型掺杂剂的器件层，以及与每个器件层的漏极区域的公共第三接触152。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：DE69332558T2

公开(公告)日：2003-09-25

申请号：DE69332558

申请日：1993-10-05

Applicant: IBM

Inventor： CHANG PAUL ,  KU EDWARD HAU-CHUN ,  COATES JOSEPH WAYNE ,  SANAYE SIMIN HOSNE

IPC: H04L12/46

Abstract: A multiport bridge includes a plurality of Bridge Port Frame Handler (BPFH) units (1'',2'',...N'') coupled through a Source Routing bus and a Transparent Bridge Bus to a microcontroller (20), a Packet Memory (12) and a Transparent Bridge Control Management System (TBCMS) (26). Each Bridge Port Frame Handler unit receives Frame from its attached LAN, forwards selected portions of Source Routing Frames to other Bridge Port Frame Handlers for further processing. Likewise, selected portions of Transparent Bridge Frames are forwarded to the TBCMS whereat routing information and signature information is extracted and returned to the forwarding BPFH unit for further processing.

公开(公告)号：DE69332558D1

公开(公告)日：2003-01-23

申请号：DE69332558

申请日：1993-10-05

Applicant: IBM

Inventor： CHANG PAUL ,  KU EDWARD HAU-CHUN ,  COATES JOSEPH WAYNE ,  SANAYE SIMIN HOSNE

IPC: H04L12/46

Abstract: A multiport bridge includes a plurality of Bridge Port Frame Handler (BPFH) units (1'',2'',...N'') coupled through a Source Routing bus and a Transparent Bridge Bus to a microcontroller (20), a Packet Memory (12) and a Transparent Bridge Control Management System (TBCMS) (26). Each Bridge Port Frame Handler unit receives Frame from its attached LAN, forwards selected portions of Source Routing Frames to other Bridge Port Frame Handlers for further processing. Likewise, selected portions of Transparent Bridge Frames are forwarded to the TBCMS whereat routing information and signature information is extracted and returned to the forwarding BPFH unit for further processing.

公开(公告)号：CA2100543A1

公开(公告)日：1994-05-13

申请号：CA2100543

申请日：1993-07-14

Applicant: IBM

Inventor： CHANG PAUL ,  COATES JOSEPH W ,  KU EDWARD H ,  SANAYE SIMIN H

IPC: H04L12/46

Abstract: A multiport bridge includes a plurality of Bridge Port Frame Handler (BPFH) units (1'',2'',...N'') coupled through a Source Routing bus and a Transparent Bridge Bus to a microcontroller (20), a Packet Memory (12) and a Transparent Bridge Control Management System (TBCMS) (26). Each Bridge Port Frame Handler unit receives Frame from its attached LAN, forwards selected portions of Source Routing Frames to other Bridge Port Frame Handlers for further processing. Likewise, selected portions of Transparent Bridge Frames are forwarded to the TBCMS whereat routing information and signature information is extracted and returned to the forwarding BPFH unit for further processing.

公开(公告)号：BR9200413A

公开(公告)日：1992-10-13

申请号：BR9200413

申请日：1992-02-06

Applicant: IBM

Inventor： CHANG PAUL ,  DELP GARY SCOTT ,  MELEIS HANAFY EL-SAYED ,  MONTALVO RAFAEL MANTILLA ,  SEIDMAN DAVID ISRAEL ,  TANTAWY AHMED NASR-EL-DIN ,  ZUMBO DOMINICK ANTHONY

IPC: G06F13/00 ,  G06F5/06 ,  G06F13/12 ,  G06F13/38 ,  H04L12/18 ,  H04L12/56 ,  H04L29/10 ,  G06F3/00

Abstract: A generic high bandwidth adapter providing a unified architecture for data communications between buses, channels, processors, switch fabrics and/or communication networks. Data is carried by data stream packets of variable lengths, and each packet includes a header control information portion required by communication protocols used to mediate the information exchange, and normally a data portion for the data which is to be communicated. The generic high bandwidth adapter comprises a processor subsystem including a processor for processing the header control information portions of data packets. The processor has access to data packets stored in a packet memory which stores data packets arriving at four generic adapter input/output ports. The packet memory is segmented into a plurality of buffers, and each data packet is stored in one or more buffers as required by the length thereof. A generic adapter manager is provided for performing and synchronizing generic adapter management functions, including implementing data structures in the packet memory by organizing data packets in buffers, and organizing data packets into queues for processing by the processor subsystem or transfer to or from generic adapter input/output ports. Each generic adapter input/output port has associated therewith a packet memory interface providing for the transfer of data packets into and out of the packet memory, such that when a data packet is received at an input/output port, the data packet is transferred into the adapter packet memory and queued for processing.

公开(公告)号：DE102016204201A1

公开(公告)日：2016-09-22

申请号：DE102016204201

申请日：2016-03-15

Applicant: IBM

Inventor： CHANG JOSEPHINE B ,  CHANG PAUL ,  COHEN GUY M ,  GUILLORN MICHAEL A

IPC: H01L39/24 ,  H01L39/22

Abstract: Silicidierte Nanodrähte als Nanobrücken in Josephson-Kontakten. Ein supraleitender silicidierter Nanodraht wird als Weak-Link-Brücke in einem Josephson-Kontakt verwendet und ein Herstellungsverfahren wird angewendet, um silicidierte Nanodrähte herzustellen, das ein Strukturieren von zwei Kontakt-Bänken und eines rauen Nanodrahts aus einem Siliciumsubstrat, ein Umformen des Nanodrahts durch Wasserstoff-Tempern und ein Silicidieren des Nanodrahts durch Einbringen eines Metalls in die Nanodraht-Struktur aufweist.

公开(公告)号：DE102016204201B4

公开(公告)日：2017-12-28

申请号：DE102016204201

申请日：2016-03-15

Applicant: IBM

Inventor： CHANG JOSEPHINE B ,  CHANG PAUL ,  COHEN GUY M ,  GUILLORN MICHAEL A

IPC: H01L39/24 ,  B82Y10/00 ,  B82Y40/00 ,  H01L39/22

Abstract: Verfahren zum Ausbilden eines supraleitenden Weak-Link-Kontakts, wobei das Verfahren aufweist: Strukturieren einer ersten Kontakt-Bank, einer zweiten Kontakt-Bank und eines rauen Nanodrahts aus einem Siliciumsubstrat; Umformen des Nanodrahts durch Wasserstoff-Tempern; und Silicidieren des Nanodrahts durch Einbringen eines Metalls in den Nanodraht; wobei: der Nanodraht so geformt, dimensioniert, strukturiert, angeordnet und/oder verbunden ist, dass er eine Weak-Link-Brücke zwischen der ersten Kontakt-Bank und der zweiten Kontakt-Bank bildet.

公开(公告)号：GB2494012B

公开(公告)日：2014-07-23

申请号：GB201209073

申请日：2011-05-10

Applicant: IBM

Inventor： CHANG JOSEPHINE ,  CHANG PAUL ,  NARAYANAN VIJAY ,  SLEIGHT JEFFREY

IPC: H01L51/05 ,  H01L51/00

Abstract: A method of forming a self-aligned device is provided and includes depositing carbon nanotubes (CNTs) onto a crystalline dielectric substrate, isolating a portion of the crystalline dielectric substrate encompassing a location of the CNTs, forming gate dielectric and gate electrode gate stacks on the CNTs while maintaining a structural integrity thereof and forming epitaxial source and drain regions in contact with portions of the CNTs on the crystalline dielectric substrate that are exposed from the gate dielectric and gate electrode gate stacks.

公开(公告)号：GB2494012A

公开(公告)日：2013-02-27

申请号：GB201209073

申请日：2011-05-10

Applicant: IBM

Inventor： CHANG JOSEPHINE ,  CHANG PAUL ,  NARAYANAN VIJAY ,  SLEIGHT JEFFREY

IPC: H01L51/05 ,  H01L51/00

Abstract: A method of forming a self-aligned device is provided and includes depositing carbon nanotubes (CNTs) onto a crystalline dielectric substrate, isolating a portion of the crystalline dielectric substrate encompassing a location of the CNTs, forming gate dielectric and gate electrode gate stacks on the CNTs while maintaining a structural integrity thereof and forming epitaxial source and drain regions in contact with portions of the CNTs on the crystalline dielectric substrate that are exposed from the gate dielectric and gate electrode gate stacks.

公开(公告)号：DE112011101023T5

公开(公告)日：2013-01-17

申请号：DE112011101023

申请日：2011-05-10

Applicant: IBM

Inventor： CHANG PAUL ,  NARAYANAN VIJAY ,  SLEIGHT JEFFREY ,  CHANG JOSEPHINE

IPC: H01L51/05 ,  H01L51/00

Abstract: Ein Verfahren zum Bilden einer selbstausgerichteten Einheit wird bereitgestellt und beinhaltet das Abscheiden von Kohlenstoff-Nanoröhren (CNTs) auf einem kristallinen dielektrischen Substrat, das Isolieren eines Teils des einen Lageort der CNTs umschließenden kristallinen dielektrischen Substrats, das Bilden von Gate-Dielektrikums- und Gate-Elektroden-Gate-Stapeln auf den CNTs unter Beihaltung von deren struktureller Integrität und das Bilden epitaktischer Source- und Drain-Zonen in Kontakt mit Teilen der CNTs auf dem kristallinen dielektrischen Substrat, die von den Gate-Dielektrikums- und Gate-Elektroden-Gate-Stapeln freiliegen.