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公开(公告)号：JP2001023378A
公开(公告)日：2001-01-26
申请号：JP2000166957
申请日：2000-06-05
Applicant: IBM
Inventor： KUMAR MANOJ , PHAM HUY VAN
IPC: G06F12/08 , G11C11/413 , G11C15/00 , G11C15/04
Abstract: PROBLEM TO BE SOLVED: To obtain an improved cache sub-system and a cache control circuit by comprising a terminal means receiving an input signal including a mode signal indicating a clock signal and plural cache functions being able to operate, and a logic circuit performing a cache function selected by responding to a mode signal during a single clock cycle. SOLUTION: A word line driver circuit is provided with a terminal 201 arranged to that a WLRSTB(word line reset bar) signal is applied to a gate terminal of a PFET 203. Gate terminals of NFET 209, 211, 213 are arranged so that they receives an EASEL (effective address) signal, an inverted EMATCHB (effective address match) signal, and a clock signal C2 respectively. A common paint of a PFET 219 and an NFET 221 are connected to input of a common node 207 and an inverter 223. The inverter 223 supplies an output signal EMATCHWL (effective address matched word line).
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公开(公告)号：JPH11317082A
公开(公告)日：1999-11-16
申请号：JP2365499
申请日：1999-02-01
Applicant: IBM
Inventor： KUMAR MANOJ
IPC: G11C11/41 , G11C7/10 , G11C7/12 , G11C11/409 , G11C11/417 , G11C11/419 , G11C13/00
Abstract: PROBLEM TO BE SOLVED: To provide a device and a method in which accurate reading and writing operations are conducted in an electronic computer memory including a cache memory. SOLUTION: A precharge circuit 12, which is coupled to a writing driver 10, precharges bit lines 16 and 18 prior to respective reading and writing operations in response to precharge/clock signals. The precharge/clock signals are related to data propagation signals so that the lines 16 and 18 are completely precharged before a reading operation takes place. A monitoring circuit 14 coupled to the lines 16 and 18 maintains a prescribed charged-up condition while a memory cell 20, which is connected to the bit lines, is conducting a reading.
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公开(公告)号：JPH0884143A
公开(公告)日：1996-03-26
申请号：JP17901895
申请日：1995-07-14
Applicant: IBM
Inventor： KOULOHERIS JACK LAWRENCE , KUMAR MANOJ
IPC: G06F13/00 , H04L12/00 , H04N5/765 , H04N5/93 , H04N7/14 , H04N7/173 , H04N21/2183 , H04N21/222 , H04N21/262
Abstract: PROBLEM TO BE SOLVED: To provide an interactive multimedia service at low cost on a communication network. SOLUTION: A method and a device are provided for distributing multimedia/ video data from a server (host processor) to plural clients connected to a communication network. More particularly preprocessed video and multimedia data packets are stored in a switch 60 in the network. When a client desires the reception of video data and multimedia data, such a request is transmitted to the host processor. Next, the host transmits a control message to the switch 60 where the requested data are stored. These switches 60 then transmit the requested data to requesting clients. When the requested data are not stored in the switches 60, it is necessary to directly transfer these data from the server to the requesting clients.
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公开(公告)号：JP2000021180A
公开(公告)日：2000-01-21
申请号：JP3142299
申请日：1999-02-09
Applicant: IBM
Inventor： KUMAR MANOJ
IPC: G11C11/419 , G11C7/06 , G11C11/409 , G11C16/06
Abstract: PROBLEM TO BE SOLVED: To obtain a dynamic sense amplifier without necessity of an external storage mechanism for holding sensed data. SOLUTION: The dynamic sense amplifier 10 cooperatively operate with a built-in latch mechanism, and converts a signal read from a memory cell array into a digital signal. The amplifier 10 is connected to a pair of complementary data output lines. The output lines are also connected to a sense enable line in connection with a pair of complementary data lines from a data output node and a column decoder belonging to a memory cell array. The built-in latch mechanism is connected to a latch enable line to respond to a read charge state on a data line and a sense enable signal supplied to the enable line. After an intermediate charge state occurs at a data output node, a latch enable signal is supplied to the enable line. Then, the intermediate charge state is charged to a final charge state of the data output node. Thus, the final charge state of the output node generates a data signal on the output line.
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公开(公告)号：EP0713293A3
公开(公告)日：1998-07-22
申请号：EP95480138
申请日：1995-09-22
Applicant: IBM
Inventor： KUMAR MANOJ , LATTIMORE GEORGE MCNEIL , POPLAWSKI JOSEPH MICHAEL JR
IPC: H03K3/356
CPC classification number: H03K3/356008
Abstract: A self resetting CMOS (SRCMOS) circuit operates with a variable clock cycle. Circuit oscillation is avoided in either long or short clock cycles. At the same time, the circuit eliminates overlapping currents by incorporating a ground interrupt device. The reset generation path is optimized to provide a fast and narrow reset pulse. In addition, the circuit saves power.
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Patent Agency Ranking
公开(公告)号：DE112012001580T5
公开(公告)日：2014-02-06
申请号：DE112012001580
申请日：2012-03-21
Applicant: IBM
Inventor： GJERTSEN ROBERT KENNETH , KUMAR MANOJ , CRAFT DAVID JONES , KANDIRAJU GOKUL BHARGAVA
IPC: G06F15/173
Abstract: Das hierarchische Wiederherstellen von gestörten Datenverarbeitungsknoten in funktionsfähigen Datenverarbeitungsknoten in einem Cluster aus Datenverarbeitungsknoten wird verwaltet durch Initiieren eines Wiederherstellungs-Leader in einem funktionsfähigen Knoten, der Management-Informationen von den funktionsfähigen Knoten abruft und die Management-Informationen anwendet, um Dateigruppen einer Meta-Dateigruppe in einem hierarchischen Dateisystem wiederherzustellen. Die Verwendung von hierarchischen Dateigruppen in dem gesamten Cluster gewährleistet eine raschere Funktionsübernahme durch das Verteilen der Wiederherstellungslast über Datenverarbeitungsknoten und parallel dazu das Unterstützen der Wiederherstellung von Knoten.
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公开(公告)号：DE3787492T2
公开(公告)日：1994-05-11
申请号：DE3787492
申请日：1987-03-27
Applicant: IBM
Inventor： DIAS DANIEL M , KUMAR MANOJ , LIEN YEONG-CHANG L , MARUYAMA KIYOSHI
Abstract: A method of switching synchronous and asynchronous data packets through a multi-stage interconnection network (MIN), so as to insure that packets with the highest assignable priority level will never be blocked at any stage of the network. More specifically, this invention relates to a method of switching voice and data packets over the MIN wherein each of the address bits in each packet determine the connection to be established at each particular stage in the network and wherein each packet has therein a priority level. In each time slot of a frame, the priority level of the packets stored in a particular originating adapter are compared and the packet with the highest priority level in each adapter is forwarded through the MIN and routed through the MIN as described above. Also, at each subswitch at each stage of the MIN, if two or more packets request the same subswitch output, only the packet with the higher priority is forwarded to the subswitch output. A packet will be assigned the highest priority only if a corresponding packet for a given circuit connection with second highest priority level was successfully transmitted through the MIN.
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公开(公告)号：DE3787492D1
公开(公告)日：1993-10-28
申请号：DE3787492
申请日：1987-03-27
Applicant: IBM
Inventor： DIAS DANIEL M , KUMAR MANOJ , LIEN YEONG-CHANG L , MARUYAMA KIYOSHI
Abstract: A method of switching synchronous and asynchronous data packets through a multi-stage interconnection network (MIN), so as to insure that packets with the highest assignable priority level will never be blocked at any stage of the network. More specifically, this invention relates to a method of switching voice and data packets over the MIN wherein each of the address bits in each packet determine the connection to be established at each particular stage in the network and wherein each packet has therein a priority level. In each time slot of a frame, the priority level of the packets stored in a particular originating adapter are compared and the packet with the highest priority level in each adapter is forwarded through the MIN and routed through the MIN as described above. Also, at each subswitch at each stage of the MIN, if two or more packets request the same subswitch output, only the packet with the higher priority is forwarded to the subswitch output. A packet will be assigned the highest priority only if a corresponding packet for a given circuit connection with second highest priority level was successfully transmitted through the MIN.
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公开(公告)号：AT235128T
公开(公告)日：2003-04-15
申请号：AT95480100
申请日：1995-07-24
Applicant: IBM
Inventor： KOULOHERIS JACK LAWRENCE , KUMAR MANOJ
IPC: G06F13/00 , H04L12/00 , H04N5/765 , H04N5/93 , H04N7/14 , H04N7/173 , H04N21/2183 , H04N21/222 , H04N21/262 , H04L29/06 , H04Q11/04
Abstract: A method and apparatus for delivering multimedia video data from a server (host processor) to a plurality of clients connected to a communications network. More specifically, with this invention, preprocessed video and multimedia data packets are stored in switches of the network. When a client desires to receive the video and multimedia data, sends a request to the host processor which in turn sends a control message to the switches storing the requested data. These switches in turn send the requested data to the requesting client. If the data is not stored in the switches, the data must then be forwarded directly from the server to the requesting client.
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公开(公告)号：DE3786449T2
公开(公告)日：1994-01-20
申请号：DE3786449
申请日：1987-12-15
Applicant: IBM
Inventor： KUMAR MANOJ , GOYAL AMBUJ , RATHI BHARAT DEEP
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