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    3.
    发明专利
    未知

    公开(公告)号：DE68921365T2

    公开(公告)日：1995-10-05

    申请号：DE68921365

    申请日：1989-03-22

    Applicant: IBM

    Inventor： MCAULIFFE KEVIN PATRICK ,  NORTON VERN ALAN ,  PFISTER GREGORY FRANCIS ,  RATHI BHARAT DEEP

    IPC: G06F15/167 ,  G06F12/12 ,  G06F13/16 ,  G06F15/173 ,  H04L12/56 ,  G06F15/16 ,  G06F12/02 ,  G06F9/46

    Abstract: An interconnection network management architecture for use with a large shared memory multiprocessor computing system including a plurality of processors and a plurality of separately addressable main memory modules. Two parallel, interconnection networks are provided each capable of interconnecting any processor to any memory module, and each having different latency characteristics. A Hot-Spot detection means is associated with each main memory module for detecting when a particular address in that module has become a Hot Spot and includes a first memory for storing all detected Hot Spots. A diverter element is associated with each processor for selectively routing memory requests over either said first or second memory network con tingent on its status as a Hot Spot. A second memory is included in each diverter element for storing all Hot Spots detected by the detector elements. A control mechanism determines if any current main memory address is a listed Hot Spot within said second memory and, if so, causes the main memory reference to be transmitted to the memory system over a selected interconnection network. Another component of this mechanism determines if a particular address has been accessed a sufficient number of times within a given timeframe to be deemed a Hot Spot and removes Hot Spots from both the first and second memories when necessary.

    4.
    发明专利
    未知

    公开(公告)号：DE68921365D1

    公开(公告)日：1995-04-06

    申请号：DE68921365

    申请日：1989-03-22

    Applicant: IBM

    Inventor： MCAULIFFE KEVIN PATRICK ,  NORTON VERN ALAN ,  PFISTER GREGORY FRANCIS ,  RATHI BHARAT DEEP

    IPC: G06F15/167 ,  G06F12/12 ,  G06F13/16 ,  G06F15/173 ,  H04L12/56 ,  G06F15/16 ,  G06F12/02 ,  G06F9/46

    Abstract: An interconnection network management architecture for use with a large shared memory multiprocessor computing system including a plurality of processors and a plurality of separately addressable main memory modules. Two parallel, interconnection networks are provided each capable of interconnecting any processor to any memory module, and each having different latency characteristics. A Hot-Spot detection means is associated with each main memory module for detecting when a particular address in that module has become a Hot Spot and includes a first memory for storing all detected Hot Spots. A diverter element is associated with each processor for selectively routing memory requests over either said first or second memory network con tingent on its status as a Hot Spot. A second memory is included in each diverter element for storing all Hot Spots detected by the detector elements. A control mechanism determines if any current main memory address is a listed Hot Spot within said second memory and, if so, causes the main memory reference to be transmitted to the memory system over a selected interconnection network. Another component of this mechanism determines if a particular address has been accessed a sufficient number of times within a given timeframe to be deemed a Hot Spot and removes Hot Spots from both the first and second memories when necessary.

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