公开(公告)号：JPH02285832A

公开(公告)日：1990-11-26

申请号：JP6851490

申请日：1990-03-20

Applicant: IBM

Inventor： ADORIAN CHIYAARUZU FUREDERITSU ,  KURISUTOFUAA NOOMAN WAARISU ,  FUIRITSUPU JIYON MAAFUETSUTO ,  SUTEIBUN FUAANISU ,  TOOMASU UINROO ,  MAIKERU JIYON PAAMAA

IPC: H04L7/10 ,  G06F5/08 ,  H03M9/00 ,  H04L7/00 ,  H04L7/033 ,  H04L7/04 ,  H04L25/06 ,  H04L25/38

Abstract: PURPOSE: To prevent information from being lost by recognizing a sample pattern through a decoder and activating the read of the final sample in the next term from the first sample in a term determined by a receiver concerning the sample of which this pattern is read. CONSTITUTION: The samples read from a data stream at suitable intervals are sent to 5 pieces of double-step shift registers 54. The latest sample is stored in a step 56 and the oldest sample is stored in a step 58. The respective samples are separated in the 1/5 term of a data bit term. Since the pattern is recognized by logic elements 60, 62, 64, 66 and 68 composed of six wide AND gates having transducers at three position of an input part, the transition from Low to High is detected. By recognizing the pattern, phase information is applied and corresponding to this information, the sample of an object to be read can be seletected.

公开(公告)号：JPH0316450A

公开(公告)日：1991-01-24

申请号：JP6851290

申请日：1990-03-20

Applicant: IBM

Inventor： FUIRITSUPU JIYON MAAFUETSUTO ,  KURISUTOFUAA NOOMAN WAARISU

IPC: H04L25/40 ,  H04L7/04 ,  H04L25/06 ,  H04L29/08

Abstract: PURPOSE: To obtain an asynchronous series data receiver having higher operation speed by sampling data from a shift register at twice of data rate and starting the reading operation of a data bit from a storage step allocated in relation to a start bit. CONSTITUTION: Series data of data rate (f) are supplied to the shift register 2. A clock signal of clock speed 3f is also supplied to the register 2. A data value on a data line 4 is sampled during the 1st step of the register 2. When a start bit is clocked through the final storage step of the register 2, valid data is started from the 1st step of the register 2 and stored in every three storage steps. Since delay time between the output of a start bit AND gate 12 turned to a high level and a reset delay AND gate 16 turned to a high level is sufficiently long, the reading of the signal value from the register 2 to a data register 10 is completed before resetting the register 2.

公开(公告)号：JPH02297782A

公开(公告)日：1990-12-10

申请号：JP9781990

申请日：1990-04-16

Applicant: IBM

Inventor： KURISUTOFUAA NOOMAN WAARISU

IPC: G11B5/55 ,  G11B7/085 ,  G11B21/08

Abstract: PURPOSE: To reduce the access time and enhance the reliability by adjusting the movement of a data head between different position so that the data head reaches a prescribed recording position at a required speed, when a rotary part to be accessed of a rotatable data storage medium arrives at the data head. CONSTITUTION: A controller makes an adjustment, in response to the rotary position of a rotatable data storage medium, between the time required for a data head to arrive at the prescribed part of the rotatable data storage medium accessible at the data head and the time required for moving the data head between different positions. In other words, the controller increases target time by the time length corresponding to one rotation of the data storage medium, until the target time becomes larger than the minimum time for the purpose of moving between these rotary positions. As a result, adjustment is possible for a relation between the moving speed and the heat generation of a data head driving device, reducing the access time of data and enabling a more reliable operation to be attained.