公开(公告)号：AU558825B2

公开(公告)日：1987-02-12

申请号：AU2185183

申请日：1983-11-30

Applicant: IBM

Inventor： KELLEY RICHARD ALLEN ,  KURTZ HOBART LAMOREE ,  MAGRISSO ISRAEL BEN ,  QUANSTROM JACK LEO

IPC: G06F13/37 ,  G06F3/04

公开(公告)号：DE3375048D1

公开(公告)日：1988-02-04

申请号：DE3375048

申请日：1983-09-06

Applicant: IBM

Inventor： KELLEY RICHARD ALLEN ,  KURTZ HOBART LAMOREE ,  MAGRISSO ISRAEL BEN ,  QUANSTROM JACK LEO

IPC: G06F13/37 ,  G06F13/36

公开(公告)号：DE3166311D1

公开(公告)日：1984-10-31

申请号：DE3166311

申请日：1981-06-25

Applicant: IBM

Inventor： CHISHOLM DOUGLAS RODERICK ,  KURTZ HOBART LAMOREE

IPC: G06F13/14 ,  G06F12/02 ,  G06F12/06 ,  G06F13/00

Abstract: A peripheral device address assignment mechanism is described which does not require the use of plugboards or jumpers. This mechanism enables a host processor to select any desired peripheral device and set its device address to any desired value at any desired time. This is accomplished by providing each peripheral device control unit with a loadable device address register for holding the device address assigned to its peripheral device. Each device control unit is further provided with circuitry responsive to the appearance of a unique I/O command on the processor I/O bus and to the activation of a unique set of the I/O bus data lines by the processor for loading into its device address register the desired device address value as supplied thereto by the processor via the I/O bus.

公开(公告)号：MX154710A

公开(公告)日：1987-12-02

申请号：MX19841683

申请日：1983-08-17

Applicant: IBM

Inventor： KELLEY RICHARD ALLEN ,  KURTZ HOBART LAMOREE ,  MAGRISSO ISRAEL BEN ,  QUANSTROM JACK LEON

IPC: G06F13/37 ,  G06F13/14 ,  G06F13/20

公开(公告)号：AU2185183A

公开(公告)日：1984-06-28

申请号：AU2185183

申请日：1983-11-30

Applicant: IBM

Inventor： KELLEY RICHARD ALLEN ,  KURTZ HOBART LAMOREE ,  MAGRISSO ISRAEL BEN ,  QUANSTROM JACK LEO

IPC: G06F13/37 ,  G06F3/04

公开(公告)号：DE2230119A1

公开(公告)日：1973-01-25

申请号：DE2230119

申请日：1972-06-21

Applicant: IBM

Inventor： KURTZ HOBART LAMOREE ,  SMITH GLENN HOSKINS ,  WOLFF CHARLES HARRY

IPC: G06F11/00 ,  G06F11/34 ,  G06F9/18

Abstract: An event detector for providing signals to general purpose digital computer hardware and/or software when excessive time passes prior to event occurrence. The detector includes storage means to record pluralities of sensitive events together with a time by which the event must be completed and clocking and comparator means to calculate target times and detect overruns.