公开(公告)号：WO2008083906A3

公开(公告)日：2009-02-26

申请号：PCT/EP2007064261

申请日：2007-12-19

Applicant: IBM ,  IBM UK ,  BERRY ROBERT WALTER JR ,  JOHNS CHARLES RAY ,  KURUTS CHRISTOPHER

Inventor： BERRY ROBERT WALTER JR ,  JOHNS CHARLES RAY ,  KURUTS CHRISTOPHER

IPC: G06F1/32

CPC classification number: G06F1/3203 ,  G06F1/266 ,  G06F1/329 ,  G06F1/3296 ,  G06F9/3836 ,  G06F9/3869 ,  G06F9/3891 ,  Y02D10/172 ,  Y02D10/24 ,  Y02D50/20

Abstract: A power system couples to a multi-core processor to provide power to the processor. The power system throttles at least one of the cores of the processor when the power that the processor consumes from thepower systemexceeds a predetermined threshold power. The power systemmay reduce the rate of instruction issue by a particular core or clock gate a particular core to provide power throttling. The power system dynamically responds to variance of the actualoutput voltage that processor circuitryreceives from the power system in comparison to an expected output voltage over time and corrects for such variance.

Abstract translation: 电力系统耦合到多核处理器以向处理器供电。 当处理器从电力系统消耗的功率获得预定的阈值功率时，电力系统节流处理器的至少一个核心。 电力系统可以降低特定核心或时钟门指令发出的速度，以提供功率节流。 电力系统动态地响应处理器电路从电力系统接收的实际输出电压的变化，与期望的输出电压相比较，并且校正这种差异。

公开(公告)号：CA2667422A1

公开(公告)日：2008-07-17

申请号：CA2667422

申请日：2007-12-19

Applicant: IBM

Inventor： JOHNS CHARLES RAY ,  BERRY ROBERT WALTER JR ,  KURUTS CHRISTOPHER

IPC: G06F1/32

Abstract: A power system couples to a multi-core processor to provide power to the processor. The power system throttles at least one of the cores of the proce ssor when the power that the processor consumes from thepower systemexceeds a predetermined threshold power. The power systemmay reduce the rate of inst ruction issue by a particular core or clock gate a particular core to provid e power throttling. The power system dynamically responds to variance of the actualoutput voltage that processor circuitryreceives from the power system in comparison to an expected output voltage over time and corrects for such variance.

公开(公告)号：CA2667422C

公开(公告)日：2016-03-29

申请号：CA2667422

申请日：2007-12-19

Applicant: IBM

Inventor： BERRY ROBERT WALTER JR ,  JOHNS CHARLES RAY ,  KURUTS CHRISTOPHER

IPC: G06F1/32

Abstract: A power system couples to a multi-core processor to provide power to the processor. The power system throttles at least one of the cores of the processor when the power that the processor consumes from thepower systemexceeds a predetermined threshold power. The power systemmay reduce the rate of instruction issue by a particular core or clock gate a particular core to provide power throttling. The power system dynamically responds to variance of the actualoutput voltage that processor circuitryreceives from the power system in comparison to an expected output voltage over time and corrects for such variance.