公开(公告)号：CA1231445A

公开(公告)日：1988-01-12

申请号：CA481597

申请日：1985-05-15

Applicant: IBM

Inventor： LANGE RUSSELL C ,  WANG WEN-YUAN

IPC: G11C11/404 ,  G11C11/408 ,  H01L27/108 ,  G11C11/24

Abstract: HIGH SPEED MERGED CHARGE MEMORY A semiconductor memory produced in a unipolar technology includes a cell which has a diffusion storage capacitor with one overlying terminal being merged with a bit/sense line, the other capacitor terminal is a diffused region and is coupled through a word transfer device to a word line injector charge source held at a fixed voltage. To provide an organized array of these cells, each bit line cell includes a shared word line charge source held at a fixed voltage and formed at the surface of a semiconductor substrate. A diffusion storage capacitor also is formed at the surface of the semiconductor and spaced apart from the shared charge source. Information is written into each bit line capacitor by applying a voltage of either of two different magnitudes, representing 1 and 0 bits of information, to the respective bit line while a word selection pulse produces an inversion layer at the surface of the substrate between each bit line capacitor and its shared word line fixed voltage charge source. At the termination of the word pulse, the fixed voltage remains stored at the capacitor node. The capacitors having the larger voltage applied to the bit line terminal of the capacitors store the greater amount of charge. This charge can then be detected by measuring the voltage of the floating bit sense line when a word pulse again connects the fixed voltage charge source with each of its respective capacitors.

公开(公告)号：DE68922817T2

公开(公告)日：1995-11-30

申请号：DE68922817

申请日：1989-09-26

Applicant: IBM

Inventor： CHU SHAO-FU SANFORD ,  KU SAN-MEI ,  LANGE RUSSELL C ,  SHEPARD JOSEPH FRANCIS ,  TSANG PAUL JA-MIN ,  WANG WEN-YUAN

IPC: H01L21/331 ,  H01L21/60 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/732 ,  H01L29/73 ,  H01L21/82 ,  H01L21/033 ,  H01L21/285 ,  H01L21/76

Abstract: A method of forming a semiconductor device on a body of semiconductor material having a first doped region of a first conductivity type, comprising the steps of: forming a stud over the first doped region; using the stud as a mask to form a second doped region of a second conductivity type in the surface of the first doped region adjoining the stud; forming a sidewall of insulating material on the stud; forming a first device contact within the sidewall; and forming a second device contact over the second doped region adjoining the sidewall, such that the first and second electrical contacts are separated by the sidewall. In accordance with an embodiment of the present invention, the step of forming the second device contact includes the steps of forming a layer of conductive material generally conformally over the first doped region and the stud, and then planarizing the layer of conductive material to a height equal to or less than that of the sidewalls. The second contact is thus self-aligned with the first and second doped regions and the first device contact. The method of the present invention can be utilized to fabricate bipolar transistors, insulated gate transistors, and BICMOS logic including both types of transistors. It can further be used to fabricate any other type of semiconductor device which utilizes the self-aligned, closely spaced device regions and contacts of the present invention.

公开(公告)号：DE68922817D1

公开(公告)日：1995-06-29

申请号：DE68922817

申请日：1989-09-26

Applicant: IBM

Inventor： CHU SHAO-FU SANFORD ,  KU SAN-MEI ,  LANGE RUSSELL C ,  SHEPARD JOSEPH FRANCIS ,  TSANG PAUL JA-MIN ,  WANG WEN-YUAN

IPC: H01L21/331 ,  H01L21/60 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/732 ,  H01L29/73 ,  H01L21/82 ,  H01L21/033 ,  H01L21/285 ,  H01L21/76

Abstract: A method of forming a semiconductor device on a body of semiconductor material having a first doped region of a first conductivity type, comprising the steps of: forming a stud over the first doped region; using the stud as a mask to form a second doped region of a second conductivity type in the surface of the first doped region adjoining the stud; forming a sidewall of insulating material on the stud; forming a first device contact within the sidewall; and forming a second device contact over the second doped region adjoining the sidewall, such that the first and second electrical contacts are separated by the sidewall. In accordance with an embodiment of the present invention, the step of forming the second device contact includes the steps of forming a layer of conductive material generally conformally over the first doped region and the stud, and then planarizing the layer of conductive material to a height equal to or less than that of the sidewalls. The second contact is thus self-aligned with the first and second doped regions and the first device contact. The method of the present invention can be utilized to fabricate bipolar transistors, insulated gate transistors, and BICMOS logic including both types of transistors. It can further be used to fabricate any other type of semiconductor device which utilizes the self-aligned, closely spaced device regions and contacts of the present invention.

公开(公告)号：CA1300764C

公开(公告)日：1992-05-12

申请号：CA602547

申请日：1989-06-12

Applicant: IBM

Inventor： CHU SHAO-FU S ,  KU SAN-MEI ,  LANGE RUSSELL C ,  SHEPHARD JOSEPH F ,  TSANG PAUL JA-MIN ,  WANG WEN-YUAN

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/60 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/732 ,  H01L21/82 ,  H01L21/033 ,  H01L21/285

Abstract: SEMICONDUCTOR DEVICES HAVING CLOSELY SPACED DEVICE REGIONS FORMED USING A SELF ALIGNING REVERSE IMAGE FABRICATION PROCESS A method of forming a semiconductor device on a body of semiconductor material having a first doped region of a first conductivity type, comprising the steps of: forming a stud over the first doped region; using the stud as a mask to form a second doped region of a second conductivity type in the surface of the first doped region adjoining the stud; forming a sidewall of insulating material on the stud; forming a first device contact within the sidewall; and forming a second device contact over the second doped region adjoining the sidewall, such that the first and second electrical contacts are separated by the sidewall. In accordance with an embodiment of the present invention, the step of forming the second device contact includes the steps of forming a layer of conductive material generally conformally over the first doped region and the stud, and then planarizing the layer of conductive material to a height equal to or less than that of the sidewalls. The second contact is thus self-aligned with the first and second doped regions and the first device contact. The method of the present invention can be utilized to fabricate bipolar transistors, insulated gate transistors, and BICMOS logic including both types of transistors. It can further be used to fabricate any other type of semiconductor device which utilizes the self-aligned, closely spaced device regions and contacts of the present invention. FI9-87-029