公开(公告)号：WO2008055150A3

公开(公告)日：2008-06-19

申请号：PCT/US2007082988

申请日：2007-10-30

Applicant: IBM ,  ADAMS EDWARD DENNIS ,  BURNHAM JAY SANFORD ,  GOUSEV EVGENI ,  NAKOS JAMES SPIROS ,  PREUSS HEATHER ELIZABETH ,  SHEPARD JOSEPH FRANCIS

Inventor： ADAMS EDWARD DENNIS ,  BURNHAM JAY SANFORD ,  GOUSEV EVGENI ,  NAKOS JAMES SPIROS ,  PREUSS HEATHER ELIZABETH ,  SHEPARD JOSEPH FRANCIS

IPC: H01L21/31

CPC classification number: H01L21/3144 ,  H01L21/28202

Abstract: A method of forming a nitrided silicon oxide layer. The method includes: forming a silicon dioxide layer on a surface (32) of a silicon substrate (30); performing a rapid thermal nitridation of the silicon dioxide layer at a temperature of less than or equal to about 900 °C and a pressure greater than about 500 Torr to form an initial nitrided silicon oxide layer; and performing a rapid thermal oxidation or anneal of the initial nitrided silicon oxide layer at a temperature of less than or equal to about 900 °C and a pressure greater than about 500 Torr to form a nitrided silicon oxide layer (34). Also a method of forming a MOSFET with a nitrided silicon oxide dielectric layer (34).

Abstract translation: 形成氮化硅氧化物层的方法。 该方法包括：在硅衬底（30）的表面（32）上形成二氧化硅层; 在小于或等于约900℃的温度和大于约500托的压力下进行二氧化硅层的快速热氮化，以形成初始氮化氧化硅层; 并且在小于或等于约900℃的温度和大于约500托的压力下进行初始氮化硅氧化物层的快速热氧化或退火以形成氮化二氧化硅层（34）。 还有一种用氮化硅氧化物介电层（34）形成MOSFET的方法。

公开(公告)号：DE68922817T2

公开(公告)日：1995-11-30

申请号：DE68922817

申请日：1989-09-26

Applicant: IBM

Inventor： CHU SHAO-FU SANFORD ,  KU SAN-MEI ,  LANGE RUSSELL C ,  SHEPARD JOSEPH FRANCIS ,  TSANG PAUL JA-MIN ,  WANG WEN-YUAN

IPC: H01L21/331 ,  H01L21/60 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/732 ,  H01L29/73 ,  H01L21/82 ,  H01L21/033 ,  H01L21/285 ,  H01L21/76

Abstract: A method of forming a semiconductor device on a body of semiconductor material having a first doped region of a first conductivity type, comprising the steps of: forming a stud over the first doped region; using the stud as a mask to form a second doped region of a second conductivity type in the surface of the first doped region adjoining the stud; forming a sidewall of insulating material on the stud; forming a first device contact within the sidewall; and forming a second device contact over the second doped region adjoining the sidewall, such that the first and second electrical contacts are separated by the sidewall. In accordance with an embodiment of the present invention, the step of forming the second device contact includes the steps of forming a layer of conductive material generally conformally over the first doped region and the stud, and then planarizing the layer of conductive material to a height equal to or less than that of the sidewalls. The second contact is thus self-aligned with the first and second doped regions and the first device contact. The method of the present invention can be utilized to fabricate bipolar transistors, insulated gate transistors, and BICMOS logic including both types of transistors. It can further be used to fabricate any other type of semiconductor device which utilizes the self-aligned, closely spaced device regions and contacts of the present invention.

公开(公告)号：DE3278798D1

公开(公告)日：1988-08-25

申请号：DE3278798

申请日：1982-04-27

Applicant: IBM

Inventor： FATULA JOSEPH JOHN ,  GARBARINO PAUL LOUIS ,  SHEPARD JOSEPH FRANCIS

IPC: H01L27/10 ,  H01L21/306 ,  H01L21/336 ,  H01L21/762 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108 ,  H01L29/78 ,  H01L21/76 ,  H01L21/28 ,  H01L27/08

Abstract: A dielectrically isolated region (16) of a mono-crystalline substrate (10), which has a orientation, has a drain region of a field effect transistor (FET) in a surface having a (100) crystal orientation with the drain region being of opposite conductivity to the conductivity of the substrate (10). A gate channel extends into the substrate (10) from the drain region and is surrounded at its upper end by the drain region. An enlarged recess (37) extends into the substrate (10) beneath the gate channel and has its walls (38) of opposite conductivity to the conductivity of the substrate (10) to form a source region and a plate of a capacitor when the FET is part of a storage cell. The source region has its upper end surrounded by the gate channel.

公开(公告)号：DE3279672D1

公开(公告)日：1989-06-08

申请号：DE3279672

申请日：1982-07-23

Applicant: IBM

Inventor： PLISKIN WILLIAM AARON ,  RISEMAN JACOB ,  SHEPARD JOSEPH FRANCIS

IPC: H01L21/70 ,  H01L21/31 ,  H01L21/3105 ,  H01L21/316 ,  H01L21/331 ,  H01L21/76 ,  H01L21/762 ,  H01L29/73

Abstract: A method is described for forming the recessed dielectric isolation in a silicon substrate. This method involves first forming trenches (16) which are less than 1 micron in depth in areas of one principal surface of the silicon substrate where isolation is desired. Where, for example, an NPN bipolar transistor structure is planned to be formed it is usually necessary to have a P+ region (6) underneath the recessed dielectric isolation to allow full isolation between the various bipolar transistor devices. A PNP transistor uses an N+ region underneath the isolation. Where a field effect transistor is planned a channel stop (30) can be substituted for the P+ region. Under the circumstance of bipolar devices, the P+ region (6) is formed in the substrate (2) prior to the deposition of an epitaxial layer (8) thereover. The trench formation is caused to be formed through the epitaxial layer and into the P+ regions therein. The surface of the trenches (16) are then oxidized in an oxidizing ambient to form a silicon dioxide layer (18) thereon. A glass (20) is deposited over this principal surface. The glass used has a thermal coefficient of expansion that approximates that of silicon and has a softening temperature of less than 1200°C. The structure is then heated to a temperature that allows the flow of the deposited glass on the surface so as to fill the trenches. The glass on the principal surface above the trench can be removed by a reactive ion etching method. Alternatively and preferably, the glass is removed from areas other than the immediate area of the trench by lithography and etching techniques followed by a second heating of the structure to cause the glass flow to result in surface planarization.

公开(公告)号：DE3469245D1

公开(公告)日：1988-03-10

申请号：DE3469245

申请日：1984-11-06

Applicant: IBM

Inventor： SHEPARD JOSEPH FRANCIS

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/768 ,  H01L23/532 ,  H01L29/45 ,  H01L29/49 ,  H01L23/48 ,  H01L21/60 ,  H01L21/28

Abstract: A method for making contact to a small area field effect transistor device is described. A monocrystalline semiconductor body (10) having at least a surface region of a first conductivity type is provided with an insulating layer (14) over the surtace region. A substantially horizontal first conductive layer (16) is formed over the insulating layer. The insulating and first conductive layers are masked and etched to form openings in the layers to the semiconductor body where the source (26), drain (28) and gate region of the device is to be formed. The openings have substantially vertical surfaces on the layered structure. A conformal, highly doped conductive layer (20, 22) of the first conductivity type is formed over the openings having these substantially vertical surfaces and over the insulating and conductive layers. The conformal conductive layer is anisotropically etched to substantially remove the horizontal portions of the conformal layer while leaving the openings with a substantially vertical conformal conductive layer on the sides thereof. The semiconductor body with the layered structure thereon is heated at a suitable temperature to cause the dopant of a second conductivity type to diffuse into the semiconductor body from the conformal conductive layer to form the source (26) and drain (28) regions and a first insulating layer (24) upon the surface of the first conductive layer and the conformal conductive layer. A second insulating layer (36) is formed over the vertical conformal conductive layer. Then a gate dielectric (40) is formed upon the surface of the semiconductor body between the source and drain regions. Electrical contacts (52, 56) are made to the first conductive layer through the first insulator layer (24) which effectively make electrical contact to the source and drain regions via the horizontal conductive layer and the vertical conformal conductive layer.

公开(公告)号：DE68922817D1

公开(公告)日：1995-06-29

申请号：DE68922817

申请日：1989-09-26

Applicant: IBM

Inventor： CHU SHAO-FU SANFORD ,  KU SAN-MEI ,  LANGE RUSSELL C ,  SHEPARD JOSEPH FRANCIS ,  TSANG PAUL JA-MIN ,  WANG WEN-YUAN

IPC: H01L21/331 ,  H01L21/60 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/732 ,  H01L29/73 ,  H01L21/82 ,  H01L21/033 ,  H01L21/285 ,  H01L21/76

Abstract: A method of forming a semiconductor device on a body of semiconductor material having a first doped region of a first conductivity type, comprising the steps of: forming a stud over the first doped region; using the stud as a mask to form a second doped region of a second conductivity type in the surface of the first doped region adjoining the stud; forming a sidewall of insulating material on the stud; forming a first device contact within the sidewall; and forming a second device contact over the second doped region adjoining the sidewall, such that the first and second electrical contacts are separated by the sidewall. In accordance with an embodiment of the present invention, the step of forming the second device contact includes the steps of forming a layer of conductive material generally conformally over the first doped region and the stud, and then planarizing the layer of conductive material to a height equal to or less than that of the sidewalls. The second contact is thus self-aligned with the first and second doped regions and the first device contact. The method of the present invention can be utilized to fabricate bipolar transistors, insulated gate transistors, and BICMOS logic including both types of transistors. It can further be used to fabricate any other type of semiconductor device which utilizes the self-aligned, closely spaced device regions and contacts of the present invention.

公开(公告)号：AU576086B2

公开(公告)日：1988-08-11

申请号：AU5884686

申请日：1986-06-13

Applicant: IBM

Inventor： COOK ROBERT KIMBAL ,  SHEPARD JOSEPH FRANCIS

IPC: H01L21/302 ,  H01L21/033 ,  H01L21/3065 ,  H05K3/06

Abstract: A method is disclosed for making submicron openings in a substrate. A mesa is formed on the substrate by reactive ion etching techniques. A film is deposited over the entire structure and the mesa is selectively etched away to yield a submicron-sized opening in the film. Using the film as a mask, the substrate exposed thereby is reactively ion etched. An example is given for producing an emitter mask for a polycrystalline silicon base bipolar transistor.

公开(公告)号：IT1165429B

公开(公告)日：1987-04-22

申请号：IT2812579

申请日：1979-12-18

Applicant: IBM

Inventor： GARDINER JAMES ROBERT ,  PLISKIN WILLIAM AARON ,  REVITZ MARTIN ,  SHEPARD JOSEPH FRANCIS

IPC: H01L29/78 ,  H01L21/033 ,  H01L21/28 ,  H01L21/336 ,  H01L29/417 ,  H01L29/778 ,  H01L

Abstract: A method of making a metal-oxide-semiconductor device is disclosed. A thin silicon dioxide insulating layer is formed on the surface of a planar silicon wafer. A first layer of intrinsic polycrystalline silicon is deposited over the dioxide layer, and a second layer of doped polycrystalline silicon is deposited over the intrinsic layer, thereby forming the gate. Subsequent hot processing steps result in diffusion of a portion of the dopant from the doped polycrystalline layer into and throughout the intrinsic layer so as to dope the latter. A metal contact layer is then deposited onto the gate and in superimposed vertical alignment with respect to the thin silicon dioxide insulating layer. The instrinsic nature of the first polycrystalline layer reduces grain growth and void formation in the polycrystalline silicon and thereby prevents the silicon dioxide from being attacked by hydrofluoric acid seeping through voids in the polycrystalline layer during subsequent processing. The yield for the manufacture of devices having thin oxide gates is substantially improved.

公开(公告)号：DE2964588D1

公开(公告)日：1983-03-03

申请号：DE2964588

申请日：1979-03-29

Applicant: IBM

Inventor： GARBARINO PAUL LOUIS ,  REVITZ MARTIN ,  SHEPARD JOSEPH FRANCIS

IPC: H01L29/78 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/339 ,  H01L21/8234 ,  H01L29/762 ,  H01L21/31

Abstract: In a field effect device such as a charge coupled device or field effect transistor in which at least two levels of polycrystalline silicon conductors are used; these two levels of polycrystalline silicon are isolated from one another with a dielectric layer. Disclosed is a dielectric layer of reflowed phosphosilicate glass (PSG) on top surfaces of a polycrystalline silicon layer which may be doped by phosphorous impurities diffusing from the PSG.

公开(公告)号：CA2105039C

公开(公告)日：1996-10-29

申请号：CA2105039

申请日：1993-08-27

Applicant: IBM

Inventor： BUTI TAQI NASSER ,  HSU LOUIS LU-CHEN ,  JOSHI RAJIV VASANT ,  SHEPARD JOSEPH FRANCIS

IPC: H01L21/3205 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/98 ,  H01L23/522 ,  H01L27/04 ,  H01L21/44 ,  H01L21/441 ,  H01L21/48

Abstract: A wafer structure suitable for the formation of semiconductor devices thereon and having a buried interconnect structure for interconnection of desired ones of the semiconductor devices according to a predetermined interconnection pattern and a method of making the same is disclosed. The wafer structure comprises a primary substrate having a first thickness appropriate for the formation of the desired semiconductor devices. The primary substrate further comprises a) conductive interconnection pads of a second thickness formed on a bottom surface of the primary substrate according to the predetermined interconnection pattern, b) first isolation pads of a third thickness formed on the bottom surface of the primary substrate between the conductive interconnection pads, and c) interconnection pad caps of a fourth thickness formed upon the surface of the interconnection pads opposite from the primary substrate, wherein the interconnection pad caps comprise a material suitable for wafer bonding, and further wherein the total thickness of the second thickness and the fourth thickness equals the third thickness. The structure further comprises a secondary substrate having an oxide layer thereon bonded to the interconnection pad caps and the first isolation pads of the primary wafer.