1.
    发明专利
    未知

    公开(公告)号:DE3888448D1

    公开(公告)日:1994-04-21

    申请号:DE3888448

    申请日:1988-09-30

    Applicant: IBM

    Abstract: Apparatus for serializing 2 parallel outputs of an all points addressable memory into successive data groups, each data group corresponding to a respective value for a pixel in an image wherein the bit-length of the pixel value is selectable, the apparatus comprising: a gate circuit having (i) 2 parallel input junctions connected to the outputs of the memory and (ii) 2 output junctions, wherein the gate circuit selectively converts each set of 2 parallel inputs at said input junctions into 2 successive data groups, each group having a bit-length of 2 bits, wherein each group is transmitted to 2 of the 2 output junctions; and a communication element for conveying to the gate circuit a signal which controls the bit-length 2 of data groups, wherein n is an integer 1

    2.
    发明专利
    未知

    公开(公告)号:DE3888448T2

    公开(公告)日:1994-10-06

    申请号:DE3888448

    申请日:1988-09-30

    Applicant: IBM

    Abstract: Apparatus for serializing 2 parallel outputs of an all points addressable memory into successive data groups, each data group corresponding to a respective value for a pixel in an image wherein the bit-length of the pixel value is selectable, the apparatus comprising: a gate circuit having (i) 2 parallel input junctions connected to the outputs of the memory and (ii) 2 output junctions, wherein the gate circuit selectively converts each set of 2 parallel inputs at said input junctions into 2 successive data groups, each group having a bit-length of 2 bits, wherein each group is transmitted to 2 of the 2 output junctions; and a communication element for conveying to the gate circuit a signal which controls the bit-length 2 of data groups, wherein n is an integer 1

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