公开(公告)号：DE69522267T2

公开(公告)日：2002-06-13

申请号：DE69522267

申请日：1995-02-03

Applicant: IBM

Inventor： FERRAIOLO FRANK DAVID ,  CAPOWSKI ROBERT STANLEY ,  CASPER DANIEL FRANCIS ,  JORDAN RICHARD CARROLL ,  LAVIOLA WILLIAM CONSTANTINO

IPC: G06F13/42 ,  H04L7/00 ,  H04L7/033 ,  G06F13/40

Abstract: A self-timed interface (STI) in which a clock signal clocks bit serial data onto a parallel, electrically conductive bus and the clock signal is transmitted on a separate line of the bus. The received data on each line of the bus is individualy phase aligned with the clock signal. The received clock signal is used to define boundary edges of a data bit cell individually for each line and the data on each line of the bus is individually phase adjusted so that, for example, a data transition position is in the center of the cell.

公开(公告)号：DE69522267D1

公开(公告)日：2001-09-27

申请号：DE69522267

申请日：1995-02-03

Applicant: IBM

Inventor： FERRAIOLO FRANK DAVID ,  CAPOWSKI ROBERT STANLEY ,  CASPER DANIEL FRANCIS ,  JORDAN RICHARD CARROLL ,  LAVIOLA WILLIAM CONSTANTINO

IPC: G06F13/42 ,  H04L7/00 ,  H04L7/033 ,  G06F13/40

Abstract: A self-timed interface (STI) in which a clock signal clocks bit serial data onto a parallel, electrically conductive bus and the clock signal is transmitted on a separate line of the bus. The received data on each line of the bus is individualy phase aligned with the clock signal. The received clock signal is used to define boundary edges of a data bit cell individually for each line and the data on each line of the bus is individually phase adjusted so that, for example, a data transition position is in the center of the cell.

公开(公告)号：CA2150744A1

公开(公告)日：1995-12-18

申请号：CA2150744

申请日：1995-06-01

Applicant: IBM

Inventor： FERRAIOLO FRANK DAVID ,  CAPOWSKI ROBERT STANLEY ,  CASPER DANIEL FRANCIS ,  JORDAN RICHARD CARROLL ,  LAVIOLA WILLIAM CONSTANTINO

IPC: G06F13/42 ,  H04L7/00 ,  H04L7/033

Abstract: A self-timed interface (STI) in which a clock signal clocks bit serial data onto a parallel, electrically conductive bus and the clock signal is transmitted on a separate line of the bus. The received data on each line of the bus is individualy phase aligned with the clock signal. The received clock signal is used to define boundary edges of a data bit cell individually for each line and the data on each line of the bus is individually phase adjusted so that, for example, a data transition position is in the center of the cell.