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Patent Agency Ranking
公开(公告)号：DE1766907A1
公开(公告)日：1974-11-21
申请号：DE1766907
申请日：1968-08-09
Applicant: IBM
Inventor： LAWRENCE BLASBALG HERMAN
Abstract: Switching circuits employing pseudo-random orthogonal or quasi-orthogonal code sequences to accomplish line to line or line group to line group switching in both a linear and nonlinear mode.
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公开(公告)号：DE1462732A1
公开(公告)日：1969-01-02
申请号：DE1462732
申请日：1966-12-24
Applicant: IBM
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公开(公告)号：DE1908031A1
公开(公告)日：1969-10-02
申请号：DE1908031
申请日：1969-02-18
Applicant: IBM
Abstract: 1,247,586. Multiplex pulse signalling. INTERNATIONAL BUSINESS MACHINES CORP. 12 March, 1969 [14 March, 1968], No. 12908/69. Heading H4L. Means are provided for combining a plurality of low speed asynchronous data channels in a high speed time division multiplex system by the use of intermediate buffer stores. General arrangement, Fig. 1. Sixteen low speed channels at different bit rates, each with its own clock signal, are supplied via interface units 100 to channel buffers 300 under the control of a time slot generator 200 which scans each of the interface units in sequence. Control circuit 400 gates the data bits from buffers 300 in accordance with a predetermined arrangement determined by the bit rates of the sixteen channels, dummy bits being introduced as required. The multiplex bit stream is then scrambled at 50 and transmitted at 60. System details.-Considering channel 1, data and clock pulses are supplied via a matching unit 112 in the interface unit 100, Fig. 2, to an AND gate 114 which gates a bi-stable 116 whenever a data and clock pulse appear together. The clock pulses control a bi-stable 118 and the outputs of both bi-stables are connected to a shift register 302, Fig. 4, in the channel buffer 300. The output of bi-stable 118 is also supplied to the left of a bidirectional counter 304 to cause it to count up, pulses applied to the right causing it to count down. The contents of the counter are decoded in a matrix 306 which controls gates 308 when a full count of 200 is reached and sets a bi-stable 310 when the count is 100. The bi-stable 310 is reset when the transmission is ended. The number of stages required for the shift register &c. is calculated to suit the corresponding channel. During the time that bi-stable 310 is set, channel 1 clock pulses are supplied via AND gate 312 to the gates 308, so that data from the shift register passes via OR gates 314 to gates 402, 404 in the control circuit 400, Fig. 5. The output of gate 312 is supplied to the count down input of counter 304 to ensure that data is always gated from the last information containing position in register 302. Data is read from each of the buffers 300 at varying rates dependent upon the data rate of the corresponding input channel so that the bits for a particular channel will occupy certain positions in the multiplexed bit stream but these positions will differ for each bit rate. For example, assuming that channel 1 data enters at a rate of 64-2 bits per second and data from the 16 channels is transmitted as 16 bit blocks, Fig. 3b (not shown), then 64.2 bits per second can be expressed as a whole number, i.e. 642 bits over a 10 second period. During each second, 70 bit positions are available for channel 1 and the transmission pattern is as follows. In the first second 64 data bits followed by 6 dummy bits are transmitted and this is repeated for the next 8 seconds. In the tenth second 66 data bits followed by 4 dummy bits are transmitted. This is repeated for 10 second intervals, 100 seconds constituting a complete frame. Other bit speeds are accommodated in similar fashion. Control circuit 400 for channel 1, Fig. 5, is arranged to gate 64 bits per second . for the first 9 seconds and 66 bits for the tenth second, AND gate 402 being activated during the first 9 seconds by signal TO from bi-stable 420 via inverter 422 and input 64 which is energized for 64 bits during each of the first nine seconds. During the tenth second AND gate 402 is inhibited and input 10 from bistable 420 activates AND gate 404 to pass 66 bits. The outputs of gates 402, 404 and the corresponding gates for the other channels are supplied via OR gate 424 to the encoder 50. The clock pulse for channel 1 time slot causes the 7 bit counter 408 to count from 1 to 75 each second interval and a decoder 410 energizes a bi-stable 416 during the count from 1 to 64 to enable gate 402. Similarly bi-stable 416 enables gate 404 during the count from 1 to 66. Output 75 of the counter activates a 4-bit counter 412 once every second and every tenth second a decoder 418 thereby enabling gate 404 and inhibiting gate 402. When no data is passed by OR gate 424 during channel 1 time slot dummy bits take the place of the data, the location of data and dummy bits being determined by the particular interconnections used for circuit 400. A similar interconnected control circuit is required at the receiver to separate the data from the dummy bits. The output of gate 424 is shown in Fig. 7A each frame comprising 100 subframes. A subframe, Fig. 7B comprises 75 blocks each containing 16 bits, five blocks containing 80 bits being reserved for synchronization purposes.
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公开(公告)号：DE1286558B
公开(公告)日：1969-01-09
申请号：DEI0032583
申请日：1966-12-22
Applicant: IBM
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公开(公告)号：DE1437511A1
公开(公告)日：1968-10-10
申请号：DE1437511
申请日：1964-07-29
Applicant: IBM
Inventor： LAWRENCE BLASBALG HERMAN
Abstract: 1,069,562. Matched filters. INTERNATIONAL BUSINESS MACHINES CORPORATION. Aug.4, 1964 [July 31, 1963], No.30674/64. Heading G1U. [Also in Division H4] A multiple-subscriber, random access communication system in which each subscriber is assigned a unique pseudo-random signal waveform, comprises a plurality of transceivers, one for each subscriber, each transceiver including a waveform recognition device responsive only to its assigned pseudo-random waveform out of a group of such waveforms, and means at each transceiver for coding any message destined for one of the subscribers into pulse form and further coding each pulse into a particular sequence of binary pulses which is transmitted as the unique waveform assigned to that subscriber. The system uses matched filter and correlation techniques and enables signals to be transmitted which overlap in time and frequency even in the presence of noise. The pseudo-random waveforms are arranged to have a low crosscorrelation function and are termed quasiorthogonal. Transmitter. As shown in Fig. 3A, a voice signal at 50 position modulates pulses from a generator 30 to supply P. P. M. train 52 to a gating network 36 controlled by a flip-flop 38 to pass either the P. P. M. message signal 52 or a signal from acquisition calling network 40 to a pseudo-noise generator 42. P. N. G. 42 converts the calling signal or the message signal into a first or a second waveform assigned to the called subscriber depending upon whether an acquisition loop 49 or message loop 47 is activated. To call a subscriber the called party's address in terms of a 17 bit binary code, for example, is entered via lead 45 into a register 44 which controls P. N. G. 42, and the acquisition network receives a signal via line 41 to actuate shift register 40b to store the 17 bit code representing the calling party's address. The code signal stored by shift register 40b is supplied to gating network 36 which is conditioned initially by flip-flop 38 to pass this code signal to P. N. G. 42. The arrangement is such that loop 49 is first activated and the called party's address signal waveform is transmitted, and then the loop 47 is activated and the calling party's address signal using the message signal waveform assigned to the called subscriber is transmitted. After the calling party's address has been transmitted and a confirmation signal has been received over lead 35 from the called subscriber, a signal from shift register 40b operates flip-flop 38 so that the P. P. M. signals 52 are converted into the message signal waveform which is shown as the pseudo-random signal sequence 42a which is generated in response to every message pulse. Each pseudo-random sequence is spaced from the next sequence in accordance with the spacing of the corresponding pulses of the P. P. M. signal 52 and is supplied via a balanced modulator 71, mixer 73 and amplifier 79 to the transmitting aerial. The pseudo-random waveforms may be provided by a shift register provided with feedback from a selected number of the stages, Fig. 4A (not shown), Stepping of the shift register being gated by the P. P. M. signals. The mixer 73 is controlled by a channel hopping unit 77 so that after the calling party's address has been transmitted over a special channel allotted for this purpose, a pseudo-noise generator 142 supplies a sequence of signals to a shift register 146 which via a digital-to-analogue convertor varies the frequency of oscillator 150. In this way all message signals are transmitted over randomly varying channels within the wideband channel. A complementary control signal is supplied via a digital-to-analogue converter 149 to the associated receiver at the calling station. When a calling party starts a calling procedure its own address is loaded into a shift register 144 via line 145 and this controls the starting point of the pseudo-random sequence from P. M. G. 142 when a start signal appears on lead 134. Receiver, Figs. 3B, C. An acquisition receiver 100 is responsive to the calling and other supervisory signals which after limiting at 112a are supplied via a narrow band I. F. amplifier to a digital matched filter 116 which is responsive to both the acquisition code and the message code of the subscriber. The filter 116 Figs. 6A to E (not shown) is of the type comprising a shift register (81) in which the output of each stage is fed to network (83) providing the sum of all the voltages appearing across weighting resistors (82a to 82n) and producing an output on line (89) via a threshold circuit (87). A sampler and clipper (84) receives the input signal (Fig. 6B) and applies it to the shift register under the control of timing pulses (Fig. 6C). The input to the shift register is in the form of a series of positive and negative spikes (Fig. 6D) and when a complete waveform matched to the filter has been received a sharp peak (90) (Fig. 6E) is developed and passed by threshold circuit (87). The output of the filter 116, Fig. 3B in response to the acquisition signal is supplied via threshold device 120 to a gating circuit 124 controlling at 126 the sampling of the message signals which appear on output 117 of the matched filter 116 to apply these signals which constitute the calling party's address, via a further threshold circuit 128 and lead 130 to address register 44, Fig. 3A. The output of circuit 124 is also supplied via lead 134 to P. N. G. 142 of the channel hopping unit 77 so that the calling party's address stored at 44 is transmitted back as a confirmation signal in the message band. The message signal is received by a receiver 102, Fig. 3C including a mixer 113 which is controlled by signals from the associated channel hopping unit 77, a narrow band I. F. amplifier 115, a digital matched filter 119 and a demodulator 121 for the P. P. M. signals. At the calling party's message receiver 102 the confirmation signal generates a signal on line 133 for application via lead 35 to the gating circuit 36 and also via lead 134 to start P. N. G. 142. The calling party's address has also been loaded via line 130 into shift register 144 of the called party to control the starting point of its P.N.G. 142, in this case the mixer 73 being controlled by digital-to-analogue converter 149 and mixer 113 by digital-to-analogue converter 148. The demodulator 121 may be a synchronous detector, Fig. 3D (not shown).
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