公开(公告)号：CA1049155A

公开(公告)日：1979-02-20

申请号：CA278400

申请日：1977-05-13

Applicant: IBM

Inventor： LEE JAMES H ,  SATYA AKELLA V S ,  LESSMANN BERND K S

IPC: H01L21/822 ,  G01R31/28 ,  H01L21/331 ,  H01L21/66 ,  H01L23/544 ,  H01L27/04 ,  H01L29/73 ,  H01L21/68

Abstract: INTEGRATED CIRCUIT ?ST STRUCTURE A complex test structure for integrated, semiconductor circuits in which the impurity regions of the test device are elongated, preferably in serpentine fashion. The elongated impurity regions emulate corresponding regions in regular integrated circuit devices. Additional regions are provided, each in elongated form, which, when impressed with appropriate voltage or currents, provide indications of defect evels and product yield in the regular devices. Advantageously, the serpentine test structure is fabricated on the same wafer and with the same process steps as the regular integrated circuit chips. In one embodiment, a plurality of such monitors are provided adjacent each other in the same test site. Regions in one monitor are selectively connected to regions in another monitor and to external contact pads by contact stations disposed between each monitor.

公开(公告)号：FR2356949A1

公开(公告)日：1978-01-27

申请号：FR7716060

申请日：1977-05-18

Applicant: IBM

Inventor： LEE JAMES H ,  LESSMANN BERND K ,  SATYA AKELLA V

IPC: H01L21/822 ,  G01R31/28 ,  H01L21/331 ,  H01L21/66 ,  H01L23/544 ,  H01L27/04 ,  H01L29/73 ,  G01R31/26 ,  H01L23/56

Abstract: A complex test structure for integrated, semiconductor circuits in which the impurity regions of the test device are elongated, preferably in serpentine fashion. The elongated impurity regions emulate corresponding regions in regular integrated circuit devices. Additional regions are provided, each in elongated form, which, when impressed with appropriate voltages or currents, provide indications of defect levels and product yield in the regular devices. Advantageously, the serpentine test structure is fabricated on the same wafer and with the same process steps as the regular integrated circuit chips. In one embodiment, a plurality of such monitors are provided adjacent each other in the same test site. Regions in one monitor are selectively connected to regions in another monitor and to external contact pads by contact stations disposed between each monitor.