公开(公告)号：JP2002150771A

公开(公告)日：2002-05-24

申请号：JP2001276057

申请日：2001-09-12

Applicant: IBM

Inventor： LEE KON WAN ,  LOUIS L SHEW

IPC: G06F12/00 ,  G06F12/08 ,  G11C11/401 ,  G11C11/406

Abstract: PROBLEM TO BE SOLVED: To refresh data in a DRAM cache memory in a computer system without generating disadvantage (e.g. delay in a processor). SOLUTION: When a desired address outputted from the processor is detected, a normal refreshing operation is stopped, the desired address is compared with a TAG address stored in a TAG memory 192 and selected by the processor, a refresh address to be generated on the basis of the oldness of data is generated in order to refresh data stored in the cache memory, reading/writing operation for a word line accessed by the desired address is executed, and data on the word line accessed by the refresh address are refreshed to execute the data refreshing operation of the DRAM cache memory. In this case, the reading/ writing operation and the data refreshing operation are simultaneously executed.

公开(公告)号：JP2002055732A

公开(公告)日：2002-02-20

申请号：JP2001170952

申请日：2001-06-06

Applicant: IBM

Inventor： LOUIS L SHEW ,  LEE KON WAN

IPC: G06F1/10 ,  G06F1/12 ,  H03K5/156

Abstract: PROBLEM TO BE SOLVED: To provide an improved clock generator whose clock skew is reduced. SOLUTION: A clock generator includes a waveform generator and a de-skew circuit. A waveform generator is clock-operated according to an input clock signal, and generates a waveform signal. The de-skew circuit is connected to the waveform generator, and generates an output clock signal by gate- controlling the waveform signal from the waveform generator with the input clock signal so that the skew of an output clock signal can be made smaller than the input clock signal.