公开(公告)号：JP2004080031A

公开(公告)日：2004-03-11

申请号：JP2003288276

申请日：2003-08-06

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CLEVENGER LAWRENCE A ,  LOUIS L SHEW ,  WONG KWONG HON

IPC: H01L27/10 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8242 ,  H01L27/06 ,  H01L27/108 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L21/28194 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28114 ,  H01L27/0629 ,  H01L27/10805 ,  H01L27/1085 ,  H01L27/10885 ,  H01L29/42376 ,  H01L29/495 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/66545

Abstract: PROBLEM TO BE SOLVED: To offer an integrated circuit structure comprising a pair of capacitors, which respectively have metal plates separated by an insulator, and a metal-gate semiconductor transistor which is electrically connected to the capacitors.
SOLUTION: Each metal gate of a transistor and one of the metal plates of each capacitor have the same metal level in an integrated circuit structure. A more detailed description is that each capacitor described above comprises a vertical capacitor which has an upper metal plate vertically above a lower metal plate, and each metal gate of the transistor and the upper metal plate of each capacitor have the same metal level in the integrated circuit structure.
COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2008282516A

公开(公告)日：2008-11-20

申请号：JP2008063543

申请日：2008-03-13

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHEN HOWARD H ,  FIFIELD JOHN A ,  LOUIS L SHEW ,  TANG HENRY H K

IPC: G11C29/56 ,  G01T1/17 ,  G01T1/24 ,  G11C11/4091 ,  H01L21/8242 ,  H01L27/108

CPC classification number: G11C11/406 ,  G01R31/31816 ,  G11C11/401 ,  G11C11/40615 ,  G11C11/4078 ,  G11C11/4091 ,  G11C29/026 ,  G11C29/028 ,  G11C29/50 ,  G11C29/52 ,  G11C2029/5002

Abstract: PROBLEM TO BE SOLVED: To provide a programmable sensing device and a method and a DRAM array for detecting soft errors.
SOLUTION: The programmable heavy-ion sensing device for accelerated DRAM soft error detection is provided. From the viewpoint of design, it is desirable to use a DRAM-based alpha particle sensing apparatus as an accelerated on-chip SER test vehicle. The sensing apparatus is provided with a programmable sensing margin, a refresh rate, and a supply voltage for attaining various degrees of SER sensitivity. In addition, a dual-mode DRAM array is proposed so that at least a portion of the array can be used to monitor high-energy particle activities, during a soft-error detection (SED) mode.
COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供可编程感测装置以及用于检测软错误的方法和DRAM阵列。

解决方案：提供用于加速DRAM软错误检测的可编程重离子感测装置。 从设计的观点来看，期望使用基于DRAM的α粒子感测装置作为加速片上SER测试车辆。 感测装置具有可编程的感测余量，刷新率和用于获得SER灵敏度的各种程度的电源电压。 另外，提出了双模式DRAM阵列，使得在软错误检测（SED）模式期间，该阵列的至少一部分可用于监视高能量粒子活动。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2003007084A

公开(公告)日：2003-01-10

申请号：JP2002116365

申请日：2002-04-18

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： LOUIS L SHEW ,  WANG LI-KONG

IPC: G06F12/08 ,  G06F12/16 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G11C29/24

CPC classification number: G11C29/808 ,  G11C29/24 ,  G11C2207/104

Abstract: PROBLEM TO BE SOLVED: To provide a new microcell redundancy system for a wide band width embedded DRAM having a SRAM cache interface.
SOLUTION: For each bank of microcell array units comprising the eDRAM, at least one microcell unit is prepared as the redundancy to replace a defected microcell within the bank. After array testing, any defective microcell inside the bank is replaced with a redundancy microcell for that bank. A fuse bank structure implementing a lookup table is established for recording each redundant microcell address and its corresponding repaired microcell address. In order to allow simultaneous multi-bank operation, the redundant microcells may only replace the defective microcells within the same bank.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：为具有SRAM缓存接口的宽带宽嵌入式DRAM提供新的微单元冗余系统。 解决方案：对于包含eDRAM的每个微单元阵列单元组，至少准备一个微单元单元作为冗余来代替存储体内的缺陷微单元。 在阵列测试之后，银行内的任何有缺陷的微单元被替换为该银行的冗余微单元。 建立实现查找表的熔丝库结构，用于记录每个冗余的微单元地址及其对应的修复的微单元地址。 为了允许同时多行操作，冗余微单元可以仅替换同一个存储体内的有缺陷的微单元。

公开(公告)号：JP2003037188A

公开(公告)日：2003-02-07

申请号：JP2002142692

申请日：2002-05-17

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： CLEVENGER LAWRENCE A ,  LOUIS L SHEW ,  RADENS CARL J ,  SHEPARD JR JOSEPH F

IPC: H01L27/108 ,  H01L21/02 ,  H01L21/8242 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L27/1085 ,  H01L27/10861 ,  H01L27/10867 ,  H01L27/10873 ,  H01L27/1203 ,  H01L28/55

Abstract: PROBLEM TO BE SOLVED: To provide a method, as well as structure, for manufacturing a dynamic random access memory device and a related transistor at the same time.
SOLUTION: A channel region and a capacitor opening are formed in a substrate by this method. Then a capacitor conductor is allowed to stick to the capacitor opening. A single insulator layer is formed above the channel region and the capacitor conductor at the same time. The single insulator layer contains a capacitor node dielectrics above the capacitor conductor while a gate dielectrics above the channel region. A single conductor layer is patterned above the single insulator layer at the same time. The single conductor layer contains a gate conductor above the gate dielectrics while a ground plate above the capacitor node dielectrics.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：提供用于同时制造动态随机存取存储器件和相关晶体管的方法以及结构。 解决方案：通过该方法在衬底中形成沟道区和电容器开口。 然后允许电容器导体粘附到电容器开口。 在通道区域和电容器导体上同时形成单个绝缘体层。 单个绝缘体层在电容器导体上方包含电容器节点电介质，而沟道区域之上的栅极电介质。 单个导体层同时在单个绝缘体层上形成图案。 单导体层包含位于栅极电介质上方的栅极导体，而电容器节点电介质上方的接地板。

公开(公告)号：JP2002150771A

公开(公告)日：2002-05-24

申请号：JP2001276057

申请日：2001-09-12

Applicant: IBM

Inventor： LEE KON WAN ,  LOUIS L SHEW

IPC: G06F12/00 ,  G06F12/08 ,  G11C11/401 ,  G11C11/406

Abstract: PROBLEM TO BE SOLVED: To refresh data in a DRAM cache memory in a computer system without generating disadvantage (e.g. delay in a processor). SOLUTION: When a desired address outputted from the processor is detected, a normal refreshing operation is stopped, the desired address is compared with a TAG address stored in a TAG memory 192 and selected by the processor, a refresh address to be generated on the basis of the oldness of data is generated in order to refresh data stored in the cache memory, reading/writing operation for a word line accessed by the desired address is executed, and data on the word line accessed by the refresh address are refreshed to execute the data refreshing operation of the DRAM cache memory. In this case, the reading/ writing operation and the data refreshing operation are simultaneously executed.

公开(公告)号：JP2002055732A

公开(公告)日：2002-02-20

申请号：JP2001170952

申请日：2001-06-06

Applicant: IBM

Inventor： LOUIS L SHEW ,  LEE KON WAN

IPC: G06F1/10 ,  G06F1/12 ,  H03K5/156

Abstract: PROBLEM TO BE SOLVED: To provide an improved clock generator whose clock skew is reduced. SOLUTION: A clock generator includes a waveform generator and a de-skew circuit. A waveform generator is clock-operated according to an input clock signal, and generates a waveform signal. The de-skew circuit is connected to the waveform generator, and generates an output clock signal by gate- controlling the waveform signal from the waveform generator with the input clock signal so that the skew of an output clock signal can be made smaller than the input clock signal.

公开(公告)号：JP2003133317A

公开(公告)日：2003-05-09

申请号：JP2002193642

申请日：2002-07-02

Applicant: IBM

Inventor： CLEVENGER LAWRENCE A ,  LOUIS L SHEW ,  RADENS CARL J ,  WANG LI-KONG ,  WONG KEITH KWONG HON

IPC: G03F7/40 ,  H01B13/00 ,  H01L21/288 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/52 ,  H05K3/02

Abstract: PROBLEM TO BE SOLVED: To provide a more simplified substitutional method of the conventional damascene approach. SOLUTION: The cloisonne approach includes a step of coating a semiconductor substrate with a photosensitive polymer, such as pyrrole having a silver salt, aniline, etc. A conductive polymer is exposed to a wet developing solution, by using standard photolithography and the resists developing method and only conductive polymer wires are left on a substrate by removing part of the exposed conductive polymer region. Then an insulating dielectric layer is adhered to the whole structure, and conductive polymer wires are produced by planarizing an insulator by the chemical mechanical polishing (CMP). Another embodiment of this invention includes a method and structure for a self- planarizing interconnecting material containing the conductive polymer. Consequently, the number of treating steps can be reduced, as compared with the conventional technology.

公开(公告)号：JP2002117676A

公开(公告)日：2002-04-19

申请号：JP2001193378

申请日：2001-06-26

Applicant: IBM

Inventor： LOUIS L SHEW ,  RIIKON WAN

IPC: G11C11/413 ,  G11C11/403 ,  G11C11/406 ,  G11C11/407 ,  G11C11/4074 ,  G11C11/4076 ,  H01L21/822 ,  H01L27/04 ,  H02M3/07

Abstract: PROBLEM TO BE SOLVED: To provide a voltage control system and a method for keeping a voltage level generated inside a semiconductor chip. SOLUTION: The method comprises a step, in which the internal voltage supply level is sampled intermittently in a low electric power mode or a 'sleep' mode, a step in which the internal voltage supply level is compared with a prescribed voltage reference level, and a step in which a voltage supply generator is activated, when an internal voltage supply level is dropped to a level being less than the prescribed voltage reference level and the internal voltage supply level is raised. When the voltage supply level is restored to the prescribed voltage reference level, the voltage supply generator is made inactive. A sampling cycle can be adjusted appropriately according to chip conditions, chip temperature, and chip size. In one embodiment, the voltage control system and the method are performed by a DRAM circuit at refresh-operation. A voltage level, including band gap reference voltage of a DRAM, line voltage for boosted word lines, LOW voltage for word lines, HIGH voltage for bit lines, and bit line equalizing voltage is suitable for sampling.

公开(公告)号：JP2002050701A

公开(公告)日：2002-02-15

申请号：JP2001197112

申请日：2001-06-28

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： THOMAS W DAYER ,  LOUIS L SHEW ,  DAVID L KOTEKI ,  KARL J REEDENSU ,  GERHARD KUNKEL ,  LI HONG ,  YOUNG LIM ,  YON JIN PAKU

IPC: H01L21/768 ,  H01L21/8242 ,  H01L23/522 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a DRAM cell which eliminates critical photolithorgraphic fabrication steps by merging stacked capacitor construction with electrical contacts, and to provide a method of fabrication thereof. SOLUTION: It is sufficient to conduct in one lithography step to form electrical contacts, because the stacked capacitors are on the same plane as bit lines and the stacked capacitors are located in a insulating material provided between the bit lines. Unlike the conventional capacitor-over-bit line(COB) DRAM cells having the capacitors on the bit lines, this DRAM cell having capacitors adjacent to the bit lines eliminates the need to have dedicated contacts in the capacitor, making it possible to realize higher capacitance with lower global topography.