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    A four quadrant multiplier using a single amplifier in a balanced modulator circuit
    1.
    发明授权
    A four quadrant multiplier using a single amplifier in a balanced modulator circuit 失效
    在平衡调制器电路中使用单放大器的四位四分之一乘法器

    公开(公告)号：US3633005A

    公开(公告)日：1972-01-04

    申请号：US3633005D

    申请日：1970-02-26

    Applicant: IBM

    Inventor： LEIGHTON HOWARD N

    IPC: H03M1/66 ,  G06G7/16 ,  G06J1/00 ,  H03C1/54 ,  H03F3/72 ,  H03K7/02

    CPC classification number: G06J1/00 ,  H03C1/545 ,  H03F3/72 ,  H03K7/02

    Abstract: A multiplier circuit, having a relatively constant input impedance, capable of multiplying a positive or a negative input signal by a gain which is variable from a positive to a negative value by varying one control impedance. The input signal is applied to a reference input and to a signal input which includes a feedback path to provide both positive and negative products without the need for additional sign circuits or complimentary signals. The multiplier circuit can be adapted for use as a balanced modulator by providing an analog input signal and switching the control impedance between two different impedance values with a binary carrier signal.

    Abstract translation: 具有相对恒定的输入阻抗的乘法器电路能够通过改变一个控制阻抗将正输入信号或负输入信号乘以可从正值到负值的增益。 输入信号被施加到参考输入和信号输入，该信号输入包括反馈路径以提供正和负产物，而不需要额外的符号电路或互补信号。 乘法器电路可以通过提供模拟输入信号并且在二个不同阻抗值之间用二进制载波信号切换控制阻抗来适于用作平衡调制器。

    2.
    发明专利
    未知

    公开(公告)号：FR2398352A1

    公开(公告)日：1979-02-16

    申请号：FR7819404

    申请日：1978-06-20

    Applicant: IBM

    Inventor： LEIGHTON HOWARD N ,  SIVERLING MICHAEL M ,  WILFINGER RAYMOND J

    IPC: G06K9/38 ,  G06K9/00

    Abstract: An array of optically sensitive devices senses printed matter with each device in the array producing an output signal representing a single black or white element in a multi-element picture being sensed by the whole array. These output signals are fed into an analog charge transfer shift register and passed serially in a fixed sequence through an output stage of the shift register. As the signal from each device passes through this output stage the device becomes what is hereafter referred to as the device of interest and the signal produced by it is analyzed to determine whether it is a black or white element. Other output stages simultaneously sense data from devices located around the device of interest to define a subarray within the original detected array while the last of these output stages is fed to a peak comparator to sense the brightest and darkest matter detected in the recent past by any element of the array. The results of these sensings are processed in accordance with a preselected algorithm to generate a digital signal wich is an indication of whether the device of interest has detected black or white.

    5.
    发明专利
    未知

    公开(公告)号：FR2414830A1

    公开(公告)日：1979-08-10

    申请号：FR7836583

    申请日：1978-12-20

    Applicant: IBM

    Inventor： DUBIL JAMES F ,  FALCOZ ALAIN M ,  GLAISE RENE J ,  JACQUART CHRISTIAN A ,  LEIGHTON HOWARD N ,  RISO VLADIMIR ,  WILFINGER RAYMOND J

    IPC: H03H15/02 ,  H03K

    Abstract: This specification describes a charge-transfer device transversal filter chip in which an input signal is fed in parallel into a number of channels the outputs of which are summed together to provide the desired transversal filter transfer function. Each channel contains an analog shift register, a signal splitter and a polarity selector. The shift registers are of unequal length to provide a different delay thru each channel. The signal splitter provides a plurality of signal paths thru each channel while the polarity selector determines whether a given path in a given channel is added or subtracted in the summation to determine the gain of the given channel in the summation.

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