公开(公告)号：DE3689797D1

公开(公告)日：1994-05-26

申请号：DE3689797

申请日：1986-05-13

Applicant: IBM

Inventor： LEMBACH ROBERT FRANCIS ,  LEWIS STEVEN DEAN ,  WILLIAMS ROBERT RUSSELL

IPC: H03K19/00 ,  G06F17/50 ,  H03K19/0175 ,  G06F15/60

Abstract: @ A method of optimizing signal timing delays and power consumption through multi-path LSI circuits constructed from a plurality of circuit blocks, each circuit block having associated therewith a plurality of power levels which are selectable to control the timing delays through the circuit block, wherein the method steps include the formation of a power- performance derivative for each circuit block, identifying therefrom the relative contribution to signal delay of the circuit block in the entire multi-path configuration, and selecting the optimum power level for an overall multi-path minimum signal delay condition, through a process of iterative calculation of timing delays through individual circuit blocks and multi-path timing analysis.

公开(公告)号：DE3689797T2

公开(公告)日：1994-11-24

申请号：DE3689797

申请日：1986-05-13

Applicant: IBM

Inventor： LEMBACH ROBERT FRANCIS ,  LEWIS STEVEN DEAN ,  WILLIAMS ROBERT RUSSELL

IPC: H03K19/00 ,  G06F17/50 ,  H03K19/0175 ,  G06F15/60

Abstract: @ A method of optimizing signal timing delays and power consumption through multi-path LSI circuits constructed from a plurality of circuit blocks, each circuit block having associated therewith a plurality of power levels which are selectable to control the timing delays through the circuit block, wherein the method steps include the formation of a power- performance derivative for each circuit block, identifying therefrom the relative contribution to signal delay of the circuit block in the entire multi-path configuration, and selecting the optimum power level for an overall multi-path minimum signal delay condition, through a process of iterative calculation of timing delays through individual circuit blocks and multi-path timing analysis.