公开(公告)号：WO0055971A8

公开(公告)日：2000-11-09

申请号：PCT/US9919535

申请日：1999-08-27

Applicant: IBM

Inventor： DAVIES ANDREW DOUGLAS ,  STORINO SALVATORE N ,  TRAN JEFF V ,  WILLIAMS ROBERT RUSSELL

IPC: H01L27/08 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/786 ,  H03K19/003 ,  H03K19/094 ,  H03K19/096 ,  H03K19/20

CPC classification number: H03K19/00315 ,  H01L27/0921 ,  H03K19/094

Abstract: In brief, methods and apparatus are provided for bipolar elimination in silicon-on-insulator (SOI) domino circuits. The apparatus for bipolar elimination in silicon-on-insulator (SOI) domino circuit includes a domino silicon-on-insulator (SOI) field effect transistor (402). An input is coupled to the domino silicon-on-insulator (SOI) field effect transistor (402). A predischarging device is coupled to said domino silicon-on-insulator (SOI) field effect transistor (402). The predischarging device is activated during a precharge mode of the domino circuit, so that the SOI parasitic bipolar transistor is not activated. A dynamic input circuit (300) couples the input to the domino silicon-on-insulator (SOI) field effect transistor (402). The output of the dynamic input circuit (300) is low during the precharge mode. The output of the dynamic input circuit (300) corresponds to the input during the evaluate mode. The output of the dynamic input circuit (300) is used to gate the predischarging device.

Abstract translation: 简而言之，提供了用于绝缘体上硅（SOI）多米诺骨电路中的双极消除的方法和装置。 绝缘体上硅（SOI）多米诺骨电路中的双极消除装置包括绝缘体上硅（SOI）场效应晶体管（402）。 输入耦合到绝缘体上硅（SOI）场效应晶体管（402）。 预放电器件耦合到所述多硅绝缘体上硅（SOI）场效应晶体管（402）。 预充电器件在多米诺骨电路的预充电模式下被激活，使得SOI寄生双极晶体管不被激活。 动态输入电路（300）将输入耦合到绝缘体上硅（SOI）场效应晶体管（402）。 在预充电模式期间，动态输入电路（300）的输出为低电平。 动态输入电路（300）的输出对应于评估模式期间的输入。 动态输入电路（300）的输出用于对预充电设备进行门控。

公开(公告)号：DE3685931T2

公开(公告)日：1993-02-25

申请号：DE3685931

申请日：1986-09-09

Applicant: IBM

Inventor： DUNHAM BRADFORD ,  FITZGERALD JOSEPH MICHAEL ,  WILLIAMS ROBERT RUSSELL

IPC: H01L21/822 ,  H01L21/3205 ,  H01L21/82 ,  H01L23/52 ,  H01L23/528 ,  H01L27/02 ,  H01L27/04 ,  H01L27/118

Abstract: A VLSI chip (100) has multiple annular rings (122) of circuit cells, interspersed with annular wiring channels (123) for interconnecting the cells. Another wiring layer runs perpendicular to the rings. A central chip area (110) contains all the I/O connections (113) for the chip.

公开(公告)号：DE2723821A1

公开(公告)日：1977-12-15

申请号：DE2723821

申请日：1977-05-26

Applicant: IBM

Inventor： WILLIAMS ROBERT RUSSELL

IPC: H03K19/177 ,  G06F7/00 ,  G11C7/00

Abstract: 1516817 Logic INTERNATIONAL BUSINESS MACHINES CORP 25 April 1977 [1 June 1976] 17187/77 Heading G4H In a logic network, signals are passed from an AND array to the OR array variously through or past inverters.

公开(公告)号：DE68910243D1

公开(公告)日：1993-12-02

申请号：DE68910243

申请日：1989-07-12

Applicant: IBM

Inventor： COX DENNIS THOMAS ,  GUERTIN DAVID LEROY ,  JOHNSON CHARLES LUTHER ,  RUDOLPH BRUCE GEORGE ,  TURNER MARK ELLIOT ,  WILLIAMS ROBERT RUSSELL

IPC: G01R31/28 ,  G01R29/02 ,  G01R31/30 ,  G06F11/22 ,  G11C29/00 ,  G11C29/02 ,  G11C29/56 ,  H01L21/822 ,  H01L27/04 ,  H03K19/003

Abstract: A performance-sensing element (PSE) circuit (300) detects the actual speed of other circuits on the same chip (200) by launching a pulse into a tapped cascade of circuits on the chip, then detecting how far the pulse has progressed after a known interval. Control signals indicating circuit speed can stabilize parameters of the other circuits, such as rate of change of current (di/dt) in driver circuits, absolute delay of clock signals from one chip to another, and relative delay of multiple clock signals within the chip.

公开(公告)号：DE68916106T2

公开(公告)日：1995-01-12

申请号：DE68916106

申请日：1989-03-14

Applicant: IBM

Inventor： GRAHAM PATRICIA KAREN ,  WILLIAMS ROBERT RUSSELL

IPC: G01R31/28 ,  G01R31/3185 ,  G06F11/00 ,  G06F11/267 ,  H03K19/00 ,  H03K19/0175 ,  G06F11/26

Abstract: In an integrated circuit chip (10) utilizing CMOS technology, an embedded data bus (11) is driven by embedded three state drivers (12-15), and the bus is in turn connected to provide a drive signal to embedded receivers and similar logic devices. An embedded threshold detector (19) is provided to detect the occurrence of any invalid data signal (i.e. a non-"0" or a non-"1" signal level) on the data bus. The threshold detector's output signal is connected to off chip terminal means, to thereby enable off chip monitoring of the bus signal. The threshold detector's output signal is also ANDed with the bus signal, to thereby prevent the application of a potentially destructive invalid bus signal to the receivers and the like. Terminator circuit means provides a known invalid signal state on the bus when the bus is in its high impedance state due to all of the three state drivers being disabled.

公开(公告)号：DE3689797D1

公开(公告)日：1994-05-26

申请号：DE3689797

申请日：1986-05-13

Applicant: IBM

Inventor： LEMBACH ROBERT FRANCIS ,  LEWIS STEVEN DEAN ,  WILLIAMS ROBERT RUSSELL

IPC: H03K19/00 ,  G06F17/50 ,  H03K19/0175 ,  G06F15/60

Abstract: @ A method of optimizing signal timing delays and power consumption through multi-path LSI circuits constructed from a plurality of circuit blocks, each circuit block having associated therewith a plurality of power levels which are selectable to control the timing delays through the circuit block, wherein the method steps include the formation of a power- performance derivative for each circuit block, identifying therefrom the relative contribution to signal delay of the circuit block in the entire multi-path configuration, and selecting the optimum power level for an overall multi-path minimum signal delay condition, through a process of iterative calculation of timing delays through individual circuit blocks and multi-path timing analysis.

公开(公告)号：DE3685931D1

公开(公告)日：1992-08-13

申请号：DE3685931

申请日：1986-09-09

Applicant: IBM

Inventor： DUNHAM BRADFORD ,  FITZGERALD JOSEPH MICHAEL ,  WILLIAMS ROBERT RUSSELL

IPC: H01L21/822 ,  H01L21/3205 ,  H01L21/82 ,  H01L23/52 ,  H01L23/528 ,  H01L27/02 ,  H01L27/04 ,  H01L27/118

Abstract: A VLSI chip (100) has multiple annular rings (122) of circuit cells, interspersed with annular wiring channels (123) for interconnecting the cells. Another wiring layer runs perpendicular to the rings. A central chip area (110) contains all the I/O connections (113) for the chip.

公开(公告)号：DE3689797T2

公开(公告)日：1994-11-24

申请号：DE3689797

申请日：1986-05-13

Applicant: IBM

Inventor： LEMBACH ROBERT FRANCIS ,  LEWIS STEVEN DEAN ,  WILLIAMS ROBERT RUSSELL

IPC: H03K19/00 ,  G06F17/50 ,  H03K19/0175 ,  G06F15/60

Abstract: @ A method of optimizing signal timing delays and power consumption through multi-path LSI circuits constructed from a plurality of circuit blocks, each circuit block having associated therewith a plurality of power levels which are selectable to control the timing delays through the circuit block, wherein the method steps include the formation of a power- performance derivative for each circuit block, identifying therefrom the relative contribution to signal delay of the circuit block in the entire multi-path configuration, and selecting the optimum power level for an overall multi-path minimum signal delay condition, through a process of iterative calculation of timing delays through individual circuit blocks and multi-path timing analysis.

公开(公告)号：DE68916106D1

公开(公告)日：1994-07-21

申请号：DE68916106

申请日：1989-03-14

Applicant: IBM

Inventor： GRAHAM PATRICIA KAREN ,  WILLIAMS ROBERT RUSSELL

IPC: G01R31/28 ,  G01R31/3185 ,  G06F11/00 ,  G06F11/267 ,  H03K19/00 ,  H03K19/0175 ,  G06F11/26

Abstract: In an integrated circuit chip (10) utilizing CMOS technology, an embedded data bus (11) is driven by embedded three state drivers (12-15), and the bus is in turn connected to provide a drive signal to embedded receivers and similar logic devices. An embedded threshold detector (19) is provided to detect the occurrence of any invalid data signal (i.e. a non-"0" or a non-"1" signal level) on the data bus. The threshold detector's output signal is connected to off chip terminal means, to thereby enable off chip monitoring of the bus signal. The threshold detector's output signal is also ANDed with the bus signal, to thereby prevent the application of a potentially destructive invalid bus signal to the receivers and the like. Terminator circuit means provides a known invalid signal state on the bus when the bus is in its high impedance state due to all of the three state drivers being disabled.

公开(公告)号：DE68910243T2

公开(公告)日：1994-05-05

申请号：DE68910243

申请日：1989-07-12

Applicant: IBM

Inventor： COX DENNIS THOMAS ,  GUERTIN DAVID LEROY ,  JOHNSON CHARLES LUTHER ,  RUDOLPH BRUCE GEORGE ,  TURNER MARK ELLIOT ,  WILLIAMS ROBERT RUSSELL

IPC: G01R31/28 ,  G01R29/02 ,  G01R31/30 ,  G06F11/22 ,  G11C29/00 ,  G11C29/02 ,  G11C29/56 ,  H01L21/822 ,  H01L27/04 ,  H03K19/003

Abstract: A performance-sensing element (PSE) circuit (300) detects the actual speed of other circuits on the same chip (200) by launching a pulse into a tapped cascade of circuits on the chip, then detecting how far the pulse has progressed after a known interval. Control signals indicating circuit speed can stabilize parameters of the other circuits, such as rate of change of current (di/dt) in driver circuits, absolute delay of clock signals from one chip to another, and relative delay of multiple clock signals within the chip.