公开(公告)号：DE2262107A1

公开(公告)日：1973-06-28

申请号：DE2262107

申请日：1972-12-19

Applicant: IBM

Inventor： HILDENBRAND WALTER WILLIAM ,  LEVINE WILBUR JACK ,  MANNING STANLEY ARTHUR ,  STROMS KARL FRIEDRICH

IPC: B41J2/045 ,  B41J2/055 ,  B41J2/175 ,  H04N1/034 ,  B41J3/04

Abstract: A collapsible ink bag supplies ink at constant pressure through a manifold containing an air bubble trap, capable of venting, which manifold is connected in common to plural lines to a multiple orifice - multiple transducer fluid wave printing head of a recorder. Constant static pressure in the ink supply is provided to avoid inadvertent ejection of ink through orifices of the nozzles. The manifold contains an air bubble and the manifold inlet line has a sufficiently low resistance to flow. Its source of ink supply is free to expand and contract, and the hydraulic resistance to fluid flow in the lines to the head is sufficiently high to eliminate cross talk of waves between separate orifices. Alternatively, a built in reservoir in the head has a single low resistance connection to the source of ink supply and high resistance lines connect it to the orifices.

公开(公告)号：DE1278298B

公开(公告)日：1968-09-19

申请号：DEJ0027877

申请日：1965-04-09

Applicant: IBM

Inventor： JENSEN ROBERT ARTHUR ,  LEVINE WILBUR JACK

IPC: G08G1/081

Abstract: 1,041,682. Road signals for controlling traffic. INTERNATIONAL BUSINESS MACHINES CORPORATION. March 22, 1965 [April 28, 1964], No. 12003/65. Heading G4Q. Traffic lights 11a-11c, Fig. 1 (not shown), at different junctions are advanced by respective stepper-switches 25a-25c which receive advance signals from buffer controllers 13a-13c which control the lengths of the phases in response to instructions received from a central processor 15. Each buffer controller, Fig. 2 (not shown), comprises three six-stage binary registers 31-33 which are set in accordance with the required phase lengths by signals from the central processor. At each phase the content of the respective register is fed to a counter 57 which is counted down from its setting by clock pulses, which may be supplied from the central processor. When the counter reaches zero an advance signal is sent to the stepper switch and the register for the next phase is connected to the counter. A three-stage ring circuit 65 determines which register is connected to the counter, and its three stages are connected to three AND gates 71 which are supplied with inputs from the respective traffic lights according to the actual phase of the lights. If the actual phase differs from the required phase a circuit 73 connected to gates 71 supplies no output, and this null output is inverted to supply an output which advances the traffic lights. The buffer controllers may be offset from each other by delaying the initial clock pulses supplied by the central processor. A counter 57 is set to the required offset and counted down by the clock pulses-when the counter reaches zero an AND gate 69 is opened to allow the clock pulses to pass to counter 57.