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    DMAC ISSUE MECHANISM VIA STREAMING ID METHOD
    1.
    发明申请
    DMAC ISSUE MECHANISM VIA STREAMING ID METHOD 审中-公开
    DMAC发行机制通过流行识别方法

    公开(公告)号：WO2006011063A2

    公开(公告)日：2006-02-02

    申请号：PCT/IB2005003353

    申请日：2005-07-28

    Applicant: SONY COMPUTER ENTERTAINMENT INC ,  IBM

    Inventor： KING MATTHEW EDWARD ,  LIU PEICHUN PETER ,  MUI DAVID ,  YAMAZAKI TAKESHI

    CPC classification number: G06F13/28 ,  G06F13/3625

    Abstract: An apparatus, a method and a computer program are provided for executing Direct Memory Access (DMA) commands. A physical queue is divided into a number of virtual queues by software based on the command type, such as processor to processor, processor to Input/Output (I/0) devices, and processor to external or system memory. Commands are then assigned to a slot based on the type of DMA command: load or store. Once assigned, the commands can be executed by alternating between the slots and by utilizing round robin systems within the slots in order to provide a more efficient manner to execute DMA commands.

    Abstract translation: 提供了用于执行直接存储器访问（DMA）命令的装置，方法和计算机程序。 基于命令类型的软件将物理队列分为若干虚拟队列，例如处理器到处理器，处理器到输入/输出（I / O）设备，以及处理器到外部或系统存储器。 然后根据DMA命令的类型将命令分配给一个插槽：加载或存储。 一旦分配了这些命令，可以通过在时隙之间交替并且通过利用时隙内的循环系统来执行命令，以便提供更有效的方式来执行DMA命令。

    ESTABLISHING COMMAND ORDER IN AN OUT OF ORDER DMA COMMAND QUEUE
    2.
    发明申请
    ESTABLISHING COMMAND ORDER IN AN OUT OF ORDER DMA COMMAND QUEUE 审中-公开
    在无序的DMA命令队列中建立命令顺序

    公开(公告)号：WO2006006084A3

    公开(公告)日：2006-07-20

    申请号：PCT/IB2005003169

    申请日：2005-07-06

    Applicant: SONY COMPUTER ENTERTAINMENT INC ,  IBM

    Inventor： DAY MICHAEL NORMAN ,  JOHNS CHARLES RAY ,  LIU PEICHUN PETER ,  TRUONG THUONG QUANG ,  YAMAZAKI TAKESHI

    IPC: G06F13/28

    CPC classification number: G06F13/28

    Abstract: A method, an apparatus, and a computer program are provided for controlling memory access. Direct Memory Access (DMA) units have become commonplace in a number of bus architectures. However, managing limited system resources has become a challenge with multiple DMA units. In order to mange the multitude of commands generated and preserve dependencies, embedded flags in commands or a barrier command are used. These operations then can control the order in which commands are executed so as to preserve dependencies.

    Abstract translation: 提供了一种用于控制存储器访问的方法，装置和计算机程序。 直接存储器访问（DMA）单元在许多总线体系结构中已经司空见惯。 但是，管理有限的系统资源已成为多个DMA单元的挑战。 为了管理生成的大量命令并保留依赖关系，可以使用命令中的嵌入标志或屏障命令。 这些操作可以控制执行命令的顺序，从而保持依赖关系。

    System, method, computer program and device for communicating command parameter between processor and memory flow controller
    4.
    发明专利
    System, method, computer program and device for communicating command parameter between processor and memory flow controller 有权
    系统，方法，计算机程序和用于在处理器和存储器流量控制器之间通信命令参数的设备

    公开(公告)号：JP2007052790A

    公开(公告)日：2007-03-01

    申请号：JP2006221861

    申请日：2006-08-16

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： JOHNS CHARLES RAY ,  SWANSON TODD ,  LIU PEICHUN PETER ,  DAY MICHAEL NORMAN ,  TRUONG THUONG QUANG

    IPC: G06F15/80

    CPC classification number: G06F13/32 ,  G06F13/1642

    Abstract: PROBLEM TO BE SOLVED: To provide a system and a method for communicating command parameters between a processor and a memory flow controller. SOLUTION: This application utilizes a channel interface as a main mechanism for communication between the processor and the memory flow controller. The channel interface provides a channel for executing communication with, for instance, a processor facility, a memory flow control facility, a machine status register, and an external processor interrupt facility. When data to be read from a corresponding register by a blocking channel are not usable or there is no writing space in the corresponding register, the processor is brought into a low-power "stall" state. When the data are made usable or a space is released, the processor is automatically called via communication on the blocking channel. COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种用于在处理器和存储器流控制器之间传送命令参数的系统和方法。 解决方案：本应用程序利用通道接口作为处理器和存储器流控制器之间通信的主要机制。 通道接口提供用于执行与例如处理器设备，存储器流控制设备，机器状态寄存器和外部处理器中断设备的通信的通道。 当通过阻塞通道从对应的寄存器读取的数据不可用或在对应的寄存器中没有写入空间时，处理器进入低功率“失速”状态。 当数据可用或释放空间时，通过阻塞通道上的通信自动调用处理器。 版权所有（C）2007，JPO＆INPIT

    METHOD AND DEVICE FOR MANAGEMENT OF CACHE LINE SUBSTITUTION IN COMPUTER SYSTEM
    6.
    发明专利
    METHOD AND DEVICE FOR MANAGEMENT OF CACHE LINE SUBSTITUTION IN COMPUTER SYSTEM 失效

    公开(公告)号：JP2001043134A

    公开(公告)日：2001-02-16

    申请号：JP2000208922

    申请日：2000-07-10

    Applicant: IBM

    Inventor： LIU PEICHUN PETER ,  FRANCIS PATRICK O'CONNELL

    IPC: G06F12/08 ,  G06F12/12

    Abstract: PROBLEM TO BE SOLVED: To obtain an optimum result for a very large software application group by obtaining an improved mechanism which manages cache line substitution in a computer system. SOLUTION: A cache memory has the mechanism which manages cache line substitution. The cache memory is equipped with cache lines which are sectioned into a 1st and a 2nd group. The number of the cache lines in the 2nd group is preferably larger than that in the 1st group. A substitution logic block selects cache lines for substitution out of the cache lines of one of the two groups in an allocation cycle.

    FACILITATION OF REGISTER UPDATES IN AN OUT-OF-ORDER PROCESSOR
    7.
    发明专利
    FACILITATION OF REGISTER UPDATES IN AN OUT-OF-ORDER PROCESSOR 未知

    公开(公告)号：CA2317080A1

    公开(公告)日：2001-04-14

    申请号：CA2317080

    申请日：2000-08-28

    Applicant: IBM

    Inventor： LIU PEICHUN PETER ,  OLSON CHRISTOPHER HANS ,  MCDONALD ROBERT GREG

    IPC: G06F9/34 ,  G06F9/38 ,  G06F9/30 ,  G06F9/312 ,  G06F9/318

    Abstract: A processor including a register, an execution unit, a temporary result buffer, and a commit function circuit. The register includes at least one register bit and may include one or more sticky bits. The execution unit is suitable for executing a set of computer instructions. The temporary result buffer is configured to receive, from the execution unit, register bi t modification information provided by the instructions. The temporary result buffer is suitable for storing the modification information in set/clear pairs of bits corresponding to respective register bits of the register. The commit function circuit is configured to receive the set/clear pairs of bits from the temporary result buffer when the instruction is committed. The commit function circuit is suitable for generating an updated bit in response to receiving the set/clear pairs of bits. The update d bit is then committed to the corresponding register bit of the register.

    METHOD AND SYSTEM FOR INQUIRYING PREFETCH CACHE BY USING SNOOP PORT
    9.
    发明专利
    METHOD AND SYSTEM FOR INQUIRYING PREFETCH CACHE BY USING SNOOP PORT 失效

    公开(公告)号：JPH11328018A

    公开(公告)日：1999-11-30

    申请号：JP3523199

    申请日：1999-02-15

    Applicant: IBM

    Inventor： CHAN KIN SHING ,  HICKS DWAIN ALAN ,  LIU PEICHUN PETER ,  MAYFIELD MICHAEL JOHN ,  TUNG SHIN HSIUNG STEPHEN

    IPC: G06F12/08 ,  G06F12/10

    Abstract: PROBLEM TO BE SOLVED: To realize a method which improves the memory prefetch performance for a data cache. SOLUTION: An interleaved data cache array divided into two sub-arrays is provided and used in a data processing system. Each sub-array includes plural cache lines, and each cache line includes a selected block of data, a parity field, a contents address designation field (ECAM) including a part of the effective address for the selected block of data, a second contents address designation field (RCAM) including the real address for the selected block of data, and a data status field. An effective address port (EA) and a real address port (RA) independent of each other allow the parallel access to a cache 118 without collision in each sub-array, and sub-array arbitration logic circuit is provided for simultaneous access to one sub-array which is tried by both the effective address port (EA) and the real address port (RA).

    METHOD AND SYSTEM FOR EXECUTING CACHE COHERENCE MECHANISM TO BE UTILIZED WITHIN CACHE MEMORY HIERARCHY
    10.
    发明专利
    METHOD AND SYSTEM FOR EXECUTING CACHE COHERENCE MECHANISM TO BE UTILIZED WITHIN CACHE MEMORY HIERARCHY 失效

    公开(公告)号：JPH10254772A

    公开(公告)日：1998-09-25

    申请号：JP3458498

    申请日：1998-02-17

    Applicant: IBM

    Inventor： HICKS DWAIN ALAN ,  LIU PEICHUN PETER ,  MAYFIELD MICHAEL JOHN ,  SINGH RAJINDER PAUL

    IPC: G06F12/08

    Abstract: PROBLEM TO BE SOLVED: To provide a method for executing a cache coherence mechanism supporting an incomprehensive cache memory hierarchy by utilizing first and second state bits in primary cache memories. SOLUTION: Primary cache memories 107 and 108 and a secondary cache memory 110 are incomprehensive. In addition, the first and second state bits are given in the primary caches 107 and 108 in connection with each cache line of the primary cache. The first state bit is set only when a corresponding cache line is corrected by a write through mode and the second bit is set only when a corresponding cache line exists also in the second cache memory 110. Cache coherence between both cache memories 107 and 108 can be maintained by utilizing the first and second state bits in the primary cache memories 107 and 108 like this.

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