公开(公告)号：JP2001117770A

公开(公告)日：2001-04-27

申请号：JP2000304842

申请日：2000-10-04

Applicant: IBM

Inventor： MCDONALD ROBERT GREG ,  PEICHUN PETER RYUU ,  OLSON CHRISTOPHER HANS

IPC: G06F9/34 ,  G06F9/38

Abstract: PROBLEM TO BE SOLVED: To efficiently process plural out-of-order, speculative and optional updates for a register. SOLUTION: The register 200 includes at least one register bit and can include one or more sticky bits 201. An executing unit 204 is suitable for executing one set of computer instructions 202. A temporary result buffer 206 is constituted so as to receive register bit modification information provided by an instruction from the executing unit 204. The temporary result buffer 206 is suitable for storing the modification information in a pair of set /clear bits corresponding to individual register bits of the register. A committing function circuit is constituted so as to receive the pair of set/clear bits from the temporary result buffer 206 when the instruction is committed. The committing function circuit generates the updated bit in response to reception of the pair of set/clear bits.

公开(公告)号：JPH11259296A

公开(公告)日：1999-09-24

申请号：JP896499

申请日：1999-01-18

Applicant: IBM

Inventor： OLSON CHRISTOPHER HANS ,  BROOKS JEFFREY SCOTT

IPC: G06F9/30 ,  G06F9/32 ,  G06F9/38

Abstract: PROBLEM TO BE SOLVED: To obtain the device which executes floating-point state and control register(FPSCR) instructions with a short delay by providing an instruction queue which gives nonserialized instructions to execution logic and serialized instruction to a logic means and is connected to the logic means and execution logic. SOLUTION: A floating-point queue(FPQ) 34 supplies an FPSCR instruction directly to FPSCR execution logic 110. The FPSCR execution logic 110 executes the FPSCR instruction and updates a floating-point register(FPR) array 44 or control register 120 according to the FPSCR instruction. The FPSCR execution logic 110 is able to execute the FPSCR instruction in a single cycle without releasing a pipeline part after the FPSCR instruction. Therefore, the delay induced by passing the FPSCR instruction through a floating-point execution pipeline can be reduced.

公开(公告)号：GB2360375A

公开(公告)日：2001-09-19

申请号：GB0023163

申请日：2000-09-20

Applicant: IBM

Inventor： MCDONALD ROBERT GREG ,  LIU PEICHUN PETER ,  OLSON CHRISTOPHER HANS

IPC: G06F9/34 ,  G06F9/38

Abstract: An execution unit 204 is provided for out-of-order execution of a set of instructions 202 and outputs register bit modification information to a temporary result buffer 206 which is suitable for storing the register bit modification information 208 corresponding to an instruction in set/clear pairs (213, Fig. 7) of bits. A register 200 includes at least one register bit and may include sticky bits 201 each bit corresponding to respective set/clear pairs of the register bit modification information. A commit function circuit (209, fig 3/4) is configured to receive the set/clear pairs of bits from the temporary result buffer when the instruction is committed and generating an updated bit. The updated bit is then committed to the corresponding register bit of the register.

公开(公告)号：SG72921A1

公开(公告)日：2000-05-23

申请号：SG1999000292

申请日：1999-02-01

Applicant: IBM

Inventor： OLSON CHRISTOPHER HANS ,  BROOKS JEFFREY SCOTT

IPC: G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F9/302

Abstract: A method and system for providing direct execution of a serializing instruction in a processor (1) is disclosed. The processor (1) has the serializing instruction and a nonserializing instruction. The processor (1) includes execution logic (38, 40) having a pipeline for executing the nonserializing instruction. The processor (1) also includes logic separate (110) from the execution logic (38, 40) for executing the serializing instruction. The method and system include recognizing the serializing instruction, recognizing the nonserializing instruction, providing the nonserializing instruction to the execution logic (38, 40), and providing the serializing instruction to the separate logic (110). The serializing instruction is executed without providing the serializing instruction to the pipeline.

公开(公告)号：CA2317080A1

公开(公告)日：2001-04-14

申请号：CA2317080

申请日：2000-08-28

Applicant: IBM

Inventor： LIU PEICHUN PETER ,  OLSON CHRISTOPHER HANS ,  MCDONALD ROBERT GREG

IPC: G06F9/34 ,  G06F9/38 ,  G06F9/30 ,  G06F9/312 ,  G06F9/318

Abstract: A processor including a register, an execution unit, a temporary result buffer, and a commit function circuit. The register includes at least one register bit and may include one or more sticky bits. The execution unit is suitable for executing a set of computer instructions. The temporary result buffer is configured to receive, from the execution unit, register bi t modification information provided by the instructions. The temporary result buffer is suitable for storing the modification information in set/clear pairs of bits corresponding to respective register bits of the register. The commit function circuit is configured to receive the set/clear pairs of bits from the temporary result buffer when the instruction is committed. The commit function circuit is suitable for generating an updated bit in response to receiving the set/clear pairs of bits. The update d bit is then committed to the corresponding register bit of the register.

公开(公告)号：MX9803108A

公开(公告)日：1998-11-30

申请号：MX9803108

申请日：1998-04-21

Applicant: IBM

Inventor： OLSON CHRISTOPHER HANS ,  BROOKS JEFFREY SCOTT

IPC: G06F9/38 ,  G06F01/00

Abstract: Se describe un sistema y método para enviar una primera instruccion en un procesador. El procesador comprende una unidad de ejecucion y proporciona una pluralidad de instrucciones. La primera instruccion depende de la ejecucion de una segunda instruccion pero no requiere de otra manera ejecucion por la unidad de ejecucion. El método primero busca la segunda instruccion. El método entonces envía la primera instruccion mediante la segunda instruccion. Un aspecto del método y sistema de envía una instruccion de almacenamiento en un procesador. La instruccion de almacenamiento tiene una direccion fuente. El procesador proporciona una pluralidad de instrucciones. El método busca una instruccion de punto flotante que se proporciona antes de la instruccion de almacenamiento. La instruccion de punto flotante tiene una direccion objeto. El método entonces determina si la direccion fuente es igual a la direccion objeto. El método envía la instruccion de almacenamiento mediante la instruccion de punto flotante si la direccion fuente es igual a la direccion objeto.

公开(公告)号：CA2163691A1

公开(公告)日：1996-07-26

申请号：CA2163691

申请日：1995-11-24

Applicant: IBM

Inventor： OLSON CHRISTOPHER HANS ,  POTTER TERENCE MATTHEW ,  VADEN MICHAEL THOMAS

IPC: G06F9/46 ,  G06F9/38 ,  G06F9/44

Abstract: The distributed completion mechanism maintains complex control dependence relations between instructions in a superscalar processor without the cycle time burden associated with large sequential queue structures. There are global busses, but none of them are cycle limiting (in general, they are almost latch-to-latch paths). The cost of this completion control mechanism is a large number of tag bits associated with each instruction stage, however, in light of shrinking lithography this cost is small and takes advantage of the strengths of newer technologies.

公开(公告)号：CA2317080C

公开(公告)日：2004-06-08

申请号：CA2317080

申请日：2000-08-28

Applicant: IBM

Inventor： OLSON CHRISTOPHER HANS ,  MCDONALD ROBERT GREG ,  LIU PEICHUN PETER

IPC: G06F9/34 ,  G06F9/38 ,  G06F9/30 ,  G06F9/312 ,  G06F9/318

Abstract: A processor including a register, an execution unit, a temporary result buffer, and a commit function circuit. The register includes at least one register bit and may include one or more sticky bits. The execution unit is suitable for executing a set of computer instructions. The temporary result buffer is configured to receive, from the execution unit, register bi t modification information provided by the instructions. The temporary result buffer is suitable for storing the modification information in set/clear pairs of bits corresponding to respective register bits of the register. The commit function circuit is configured to receive the set/clear pairs of bits from the temporary result buffer when the instruction is committed. The commit function circuit is suitable for generating an updated bit in response to receiving the set/clear pairs of bits. The update d bit is then committed to the corresponding register bit of the register.

公开(公告)号：ID27634A

公开(公告)日：2001-04-19

申请号：ID20000824

申请日：2000-09-25

Applicant: IBM

Inventor： MCDONALD ROBERT GREG ,  LIU PEICHUN PETER ,  OLSON CHRISTOPHER HANS

IPC: G06F9/34 ,  G06F9/38

公开(公告)号：BR9801419A

公开(公告)日：1999-05-11

申请号：BR9801419

申请日：1998-04-22

Applicant: IBM

Inventor： OLSON CHRISTOPHER HANS

IPC: G06F9/38

Abstract: Provided are a system and method for forwarding a first instruction in a processor. The processor comprises an execution unit and provides a plurality of instructions. The first instruction depends upon execution of a second instruction but does not otherwise require execution by the execution unit. The method first searches for the second instruction and then forwards the first instruction via the second instruction. One embodiment of the method and system forwards a store instruction in a processor. The store instruction has a source address. The processor provides a plurality of instructions. The method searches for a floating point instruction that is provided before the store instruction. The floating point instruction has a target address. The method then determines if the source address is equal to the target address. The method forwards the store instruction through the floating point instruction if the source address is equal to the target address.