公开(公告)号：EP2008209A4

公开(公告)日：2011-08-03

申请号：EP07758982

申请日：2007-03-21

Applicant: IBM

Inventor： HABITZ PETER A ,  LIVINGSTONE WILLIAM J

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G06F17/5081

公开(公告)号：WO2007112240A3

公开(公告)日：2008-08-07

申请号：PCT/US2007064486

申请日：2007-03-21

Applicant: IBM ,  HABITZ PETER A ,  LIVINGSTONE WILLIAM J

Inventor： HABITZ PETER A ,  LIVINGSTONE WILLIAM J

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G06F17/5081

Abstract: Disclosed are embodiments of an interconnection array (4) for a circuit. The interconnection array comprises a victim net (100) that is positioned parallel to and adjacent to sections of multiple crossed aggressor nets (200-400), thereby, minimizing the exposure of the circuit to delay or false switching as a result of coupling capacitance. Also, disclosed are embodiments of an associated method of re-routing an interconnection array (4) that incorporates identifying a victim net (100) and at least two aggressor nets (200-400) and crossing the aggressor nets (200-400) so that sections of multiple aggressor nets are positioned parallel to and adjacent to the victim net (100) in order to minimizes the impact of coupling capacitance on the victim net (100) with minimal changes to the wiring environment.

Abstract translation: 公开了用于电路的互连阵列（4）的实施例。 互连阵列包括与多个交叉侵入网（200-400）的部分平行并相邻定位的受害网（100），从而最小化作为耦合电容的结果的延迟或假切换的电路的暴露。 此外，公开了重新路由互连阵列（4）的相关联的方法的实施例，其包括识别受害网（100）和至少两个攻击者网（200-400）并且横穿攻击者网（200-400），从而 多个攻击网的部分平行于和邻近受害网（100）定位，以便最小化对接线环境的最小化对受害网络（100）的耦合电容的影响。