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    METHOD AND SYSTEM FOR EVALUATING STATISTICAL SENSITIVITY CREDIT IN PATH-BASED HYBRID MULTI-CONRNER STATIC TIMING ANALYSIS
    3.
    发明申请
    METHOD AND SYSTEM FOR EVALUATING STATISTICAL SENSITIVITY CREDIT IN PATH-BASED HYBRID MULTI-CONRNER STATIC TIMING ANALYSIS 审中-公开
    评估基于路径混合多孔静态时序分析的统计灵敏度信誉的方法和系统

    公开(公告)号：WO2008106369A3

    公开(公告)日：2008-10-16

    申请号：PCT/US2008054689

    申请日：2008-02-22

    Applicant: IBM ,  BUCK NATHAN C ,  DUBUQUE JOHN P ,  FOREMAN ERIC A ,  HABITZ PETER A ,  KALAFALA KERIM ,  QI PEIHUA ,  VISWESWARIAH CHANDRAMOULI ,  WANG XIAOYUE

    Inventor： BUCK NATHAN C ,  DUBUQUE JOHN P ,  FOREMAN ERIC A ,  HABITZ PETER A ,  KALAFALA KERIM ,  QI PEIHUA ,  VISWESWARIAH CHANDRAMOULI ,  WANG XIAOYUE

    IPC: G06F9/45

    CPC classification number: G06F17/5031

    Abstract: Methods, systems and computer program products for analyzing a timing design of an integrated circuit are disclosed. According to an embodiment, a method for analyzing a timing design of an integrated circuit comprises: providing an initial static timing analysis of the integrated circuit; selecting a static timing test with respect to a static timing test point based on the initial static timing analysis; selecting a timing path (20, 30, 50) leading to the static timing test point for the static timing test; determining an integrated slack path variability for the timing path (20, 30, 50) based on a joint probability distribution of at least one statistically independent parameter; and analyzing the timing design based on the integrated slack path variability.

    Abstract translation: 公开了用于分析集成电路的时序设计的方法，系统和计算机程序产品。 根据一个实施例，一种用于分析集成电路的时序设计的方法包括：提供集成电路的初始静态时序分析; 基于初始静态时序分析选择关于静态时序测试点的静态时序测试; 选择通向所述静态时序测试点的时序路径（20,30,50）用于所述静态时序测试; 基于至少一个统计独立参数的联合概率分布确定所述定时路径（20,30,50）的综合松弛路径可变性; 并根据综合松弛路径变化分析时间设计。

    A METHOD OF REDUCING CORRELATED COUPLING BETWEEN NETS
    4.
    发明申请
    A METHOD OF REDUCING CORRELATED COUPLING BETWEEN NETS 审中-公开
    一种降低网络之间相关耦合的方法

    公开(公告)号：WO2007112240A3

    公开(公告)日：2008-08-07

    申请号：PCT/US2007064486

    申请日：2007-03-21

    Applicant: IBM ,  HABITZ PETER A ,  LIVINGSTONE WILLIAM J

    Inventor： HABITZ PETER A ,  LIVINGSTONE WILLIAM J

    IPC: G06F17/50

    CPC classification number: G06F17/5077 ,  G06F17/5081

    Abstract: Disclosed are embodiments of an interconnection array (4) for a circuit. The interconnection array comprises a victim net (100) that is positioned parallel to and adjacent to sections of multiple crossed aggressor nets (200-400), thereby, minimizing the exposure of the circuit to delay or false switching as a result of coupling capacitance. Also, disclosed are embodiments of an associated method of re-routing an interconnection array (4) that incorporates identifying a victim net (100) and at least two aggressor nets (200-400) and crossing the aggressor nets (200-400) so that sections of multiple aggressor nets are positioned parallel to and adjacent to the victim net (100) in order to minimizes the impact of coupling capacitance on the victim net (100) with minimal changes to the wiring environment.

    Abstract translation: 公开了用于电路的互连阵列（4）的实施例。 互连阵列包括与多个交叉侵入网（200-400）的部分平行并相邻定位的受害网（100），从而最小化作为耦合电容的结果的延迟或假切换的电路的暴露。 此外，公开了重新路由互连阵列（4）的相关联的方法的实施例，其包括识别受害网（100）和至少两个攻击者网（200-400）并且横穿攻击者网（200-400），从而 多个攻击网的部分平行于和邻近受害网（100）定位，以便最小化对接线环境的最小化对受害网络（100）的耦合电容的影响。

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