公开(公告)号：US3900746A

公开(公告)日：1975-08-19

申请号：US46656274

申请日：1974-05-03

Applicant: IBM

Inventor： KRAFT WAYNE R ,  LOWDEN ROBERT P

IPC: H03K19/0175 ,  H03K19/0185 ,  H03K19/0944 ,  H03F3/16 ,  H03F3/18 ,  H03K3/14

CPC classification number: H03K19/017518 ,  H03K19/09448

Abstract: An interface circuit utilizing bipolar and complementary field effect transistors for interfacing low voltage circuits with higher voltage circuits. The circuit input at the lower voltage level comprises a bipolar transistor connected as an emitter follower. The circuit output is a FET inverter having its input connected to the collector of the bipolar transistor. A divertable current sink in the form of a third FET is connected in series with the inverter and to the emitter of the bipolar transistor.

公开(公告)号：DE2514462A1

公开(公告)日：1975-11-13

申请号：DE2514462

申请日：1975-04-03

Applicant: IBM

Inventor： KRAFT WAYNE R ,  LOWDEN ROBERT P

IPC: H03K19/0175 ,  H03K19/0185 ,  H03K19/0944 ,  H03K5/00

Abstract: 1491059 Logic voltage-conversion interface INTERNATIONAL BUSINESS MACHINES CORP 17 March 1975 [3 May 1974] 10954/75 Heading H3T A voltage level conversion circuit has an input circuit branch comprising a bipolar transistor T1 with input signals applied to its base and a load element P2, an output circuit branch comprising a complementary FET inverter P1, N2 with the gate electrodes connected to the collector of the bipolar transistor T 1, both branches being connected to a common variable-current sink N 1 which is responsive to the potential on the collector of the bipolar transistor Tl to control the current it will sink. As shown the two branches may be connected to a common supply terminal V3, they may also be connected to two different supplies (V5, V3, Fig 3, not shown). Preferably the current sink FETN, and the FET of the inverter having the same polarity N2 have a transconductance greater than the other FET OF the inverter P1, produced by a high gatewidth to length ratio. With T 1 off, N 1 and N2 hold the output terminal C at ground level. As T 1 is turned ON, N 1 provides a low resistance path for T 1 to ground, the current raises the potential of node E which temporarily is at a higher potential than node C. Current flows through N2 in a feed forward effect and speeds up the rise time of the waveform at C. Simultaneously with Tl going ON node B is pulled down and this change turns N2 off, P 1 ON and limits the current flow in N1.

公开(公告)号：CA1047602A

公开(公告)日：1979-01-30

申请号：CA223172

申请日：1975-03-21

Applicant: IBM

Inventor： KRAFT WAYNE R ,  LOWDEN ROBERT P

IPC: H03K19/0175 ,  H03K19/0185 ,  H03K19/0944 ,  G05F1/08

Abstract: VOLTAGE LEVEL CONVERSION CIRCUIT An interface circuit utilizing bipolar and complementary field effect transistors for interfacing low voltage circuits with higher voltage circuits. The circuit input at the lower voltage level comprises a bipolar transistor connected as an emitter follower. The circuit output is a FET inverter having its input connected to the collector of the bipolar transistor. A divertable current sink in the form of a third FET is connected in series with the inverter and to the emitter of the bipolar transistor.