公开(公告)号：US3900746A

公开(公告)日：1975-08-19

申请号：US46656274

申请日：1974-05-03

Applicant: IBM

Inventor： KRAFT WAYNE R ,  LOWDEN ROBERT P

IPC: H03K19/0175 ,  H03K19/0185 ,  H03K19/0944 ,  H03F3/16 ,  H03F3/18 ,  H03K3/14

CPC classification number: H03K19/017518 ,  H03K19/09448

Abstract: An interface circuit utilizing bipolar and complementary field effect transistors for interfacing low voltage circuits with higher voltage circuits. The circuit input at the lower voltage level comprises a bipolar transistor connected as an emitter follower. The circuit output is a FET inverter having its input connected to the collector of the bipolar transistor. A divertable current sink in the form of a third FET is connected in series with the inverter and to the emitter of the bipolar transistor.

公开(公告)号：DE2514462A1

公开(公告)日：1975-11-13

申请号：DE2514462

申请日：1975-04-03

Applicant: IBM

Inventor： KRAFT WAYNE R ,  LOWDEN ROBERT P

IPC: H03K19/0175 ,  H03K19/0185 ,  H03K19/0944 ,  H03K5/00

Abstract: 1491059 Logic voltage-conversion interface INTERNATIONAL BUSINESS MACHINES CORP 17 March 1975 [3 May 1974] 10954/75 Heading H3T A voltage level conversion circuit has an input circuit branch comprising a bipolar transistor T1 with input signals applied to its base and a load element P2, an output circuit branch comprising a complementary FET inverter P1, N2 with the gate electrodes connected to the collector of the bipolar transistor T 1, both branches being connected to a common variable-current sink N 1 which is responsive to the potential on the collector of the bipolar transistor Tl to control the current it will sink. As shown the two branches may be connected to a common supply terminal V3, they may also be connected to two different supplies (V5, V3, Fig 3, not shown). Preferably the current sink FETN, and the FET of the inverter having the same polarity N2 have a transconductance greater than the other FET OF the inverter P1, produced by a high gatewidth to length ratio. With T 1 off, N 1 and N2 hold the output terminal C at ground level. As T 1 is turned ON, N 1 provides a low resistance path for T 1 to ground, the current raises the potential of node E which temporarily is at a higher potential than node C. Current flows through N2 in a feed forward effect and speeds up the rise time of the waveform at C. Simultaneously with Tl going ON node B is pulled down and this change turns N2 off, P 1 ON and limits the current flow in N1.

公开(公告)号：CA1180818A

公开(公告)日：1985-01-08

申请号：CA418005

申请日：1982-12-17

Applicant: IBM

Inventor： MOORE VICTOR S ,  VENESKI GERARD A ,  PARKER TONY E ,  RHODES JOSEPH C JR ,  KRAFT WAYNE R ,  STAHL WILLIAM L JR

IPC: G06F9/22 ,  G06F9/28

Abstract: MICROWORD CONTROL SYSTEM UTILIZING MULTIPLEXED PROGRAMMABLE LOGIC ARRAYS A microword control system is provided for producing the sequences of microwords used to control the execution of processor instructions in a microprogrammed digital data processor. This microword control system includes a plurality of programmable logic array mechanisms responsive to the processor instruction to be executed for individually producing different ones of the microwords needed to execute such instruction. This microword control system also includes microword-responsive control circuitry for controlling the operation of the data processor. This microword control system further includes mutliplexing circuitry for supplying microwords from different ones of the programmable logic array mechanisms to the control circuitry during different time intervals.

公开(公告)号：MX157488A

公开(公告)日：1988-11-25

申请号：MX19547482

申请日：1982-12-07

Applicant: IBM

Inventor： WYAM VIRGIL D ,  KRAFT WAYNE R ,  THOME NANDOR G

IPC: G06F7/00 ,  G06F9/30 ,  G06F13/40 ,  G06F15/78 ,  H01L23/52

Abstract: The signal transfer mechanism includes a plural-bit data bus (16) formed on an integrated circuit chip for transferring plural-bit binary data signals between plural-bit signal source registers (17, 18, 19, 26, 32, 35) and plural-bit signal destination registers (17, 18, 19, 26, 31, 32, 35) formed on the integrated circuit chip, and which are coupled to the plural-bit data bus (16) for respectively supplying plural-bit data signals to and receiving plural-bit data signals from the bus and a processor control unit (14) enabling one of the signal source register to put a plural-bit data signal onto the data bus (16) during a first processor control cycle and enabling one of the signal destination registers to take in this plural-bit data signal from the bus during a second and different processor control cycle. The inherent capacitance of the plural-bit data bus serves to store the plural-bit data signal during the first and second and any intervening processor control cycles.

公开(公告)号：MX154389A

公开(公告)日：1987-08-07

申请号：MX19547182

申请日：1982-12-07

Applicant: IBM

Inventor： MOORE VICTOR S ,  KRAFT WAYNE R ,  RHODES JOSEPH C JR

IPC: H03K19/177 ,  G06F9/22 ,  H03M7/00 ,  H03M7/28

Abstract: A multi-bit operation code (22) is decoded into a single product term in the AND array (20) of a programmable logic array. That single product term is then processed through a clock (45) driven sequencer (32) to generate a plurality of sequential product term signals. These sequential product terms are decoded by the OR array (30) of the programmable logic array to generate a plurality of sequential time states (58) corresponding to the decoded operation code (22).

公开(公告)号：CA1047602A

公开(公告)日：1979-01-30

申请号：CA223172

申请日：1975-03-21

Applicant: IBM

Inventor： KRAFT WAYNE R ,  LOWDEN ROBERT P

IPC: H03K19/0175 ,  H03K19/0185 ,  H03K19/0944 ,  G05F1/08

Abstract: VOLTAGE LEVEL CONVERSION CIRCUIT An interface circuit utilizing bipolar and complementary field effect transistors for interfacing low voltage circuits with higher voltage circuits. The circuit input at the lower voltage level comprises a bipolar transistor connected as an emitter follower. The circuit output is a FET inverter having its input connected to the collector of the bipolar transistor. A divertable current sink in the form of a third FET is connected in series with the inverter and to the emitter of the bipolar transistor.

公开(公告)号：CA1199415A

公开(公告)日：1986-01-14

申请号：CA440045

申请日：1983-10-31

Applicant: IBM

Inventor： THOMA NANDOR G ,  MOORE VICTOR S ,  KRAFT WAYNE R

IPC: G06F9/22 ,  G06F9/26

Abstract: MICROWORD GENERATION MECHANISM UTILIZING A SEPARATE BRANCH DECISION PROGRAMMABLE LOGIC ARRAY A microword generation mechanism is provided for producing the sequences of microwords used to control the execution of processor instructions in a microprogrammed digital data processor. This microword generation mechanism includes programmable logic array means responsive to the processor instructions for producing the appropriate microword sequences. The microword generation mechanism also includes condition indicator circuitry for supplying indicator signals indicating whether the results of arithmetic and logic operations in the processor meet certain types of conditions. The microword generation mechanism further includes a condition testing programmable logic array responsive to the condition field of a conditional branch type processor instruction for testing the appropriate indicator signal or signals and causing a branch type microword sequence to be produced if the specified condition is met.

公开(公告)号：CA1180456A

公开(公告)日：1985-01-02

申请号：CA417165

申请日：1982-12-07

Applicant: IBM

Inventor： WYATT VIRGIL D ,  KRAFT WAYNE R ,  THOMA NANDOR G

IPC: G06F7/00 ,  G06F9/30 ,  G06F13/40 ,  G06F15/78 ,  H01L23/52

Abstract: LARGE SCALE INTEGRATION DATA PROCESSOR SIGNAL TRANSFER MECHANISM A digital data signal transfer mechanism is provided for use in large scale integration digital data processor circuitry formed on an integrated circuit chip. The signal transfer mechanism includes a plural-bit data bus formed on the integrated circuit chip for transferring plural-bit binary data signals between different locations on the chip. The signal transfer mechanism also includes plural-bit signal source circuitry and plural-bit signal destination circuitry formed on the integrated circuit chip and coupled to the plural-bit data bus for respectively supplying plural-bit data signals to and receiving plural-bit data signals from the bus. The signal transfer mechanism further includes processor control circuitry coupled to the signal source and signal destination circuitry for enabling the signal source circuitry to put a plural-bit data signal onto the data bus during a first processor control cycle and for enabling the signal destination circuitry to take in this plural-bit data signal from the bus during a second and different processor control cycle. The inherent capacitance of the plural-bit data bus serves to store the plural-bit data signal during the first and second and any intervening processor control cycles.

公开(公告)号：CA1149071A

公开(公告)日：1983-06-28

申请号：CA363530

申请日：1980-10-29

Applicant: IBM

Inventor： MOORE VICTOR S ,  KRAFT WAYNE R ,  RHODES JOSEPH C JR ,  STAHL WILLIAM L JR

IPC: G06F7/00 ,  G06F9/22 ,  G06F15/78 ,  G06F3/00

Abstract: A FLEXIBLE PROCESSOR ON A SINGLE SEMICONDUCTOR SUBSTRATE A processor is provided that is fabricated on a single semiconductor substrate. The processor includes an AND array for receiving program instructions from input sources external of the processor and for generating product signals. An OR array is provided and interconnected to the AND array for receiving the product signals and for generating a plurality of control signals. A register array receives ones of the plurality of control signals and transfers data between the processor and data sources external of the processor. An arithmetic and logic unit array is also provided on the semiconductor substrate and interconnected to the register array and the OR array for executing operations on data received from the register array in accordance with ones of the plurality of control signals to generate output data. A control register is further provided and is interconnected to the OR array and the AND array for receiving ones of the plurality of control signals for controlling execution of the program instructions within the AND array.