公开(公告)号：BR8803623A

公开(公告)日：1989-02-08

申请号：BR8803623

申请日：1988-07-19

Applicant: IBM

Inventor： HWANG WEI ,  LU NICKY CHAU-CHU

IPC: H01L27/04 ,  H01L21/334 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/94 ,  G11C11/34 ,  G11C11/21

Abstract: A semiconductor memory cell structure incorporating a vertical access transistor over a trench storage capacitor including a semiconductor wafer having a semiconductor substrate (16) and an epitaxial layer (36) disposed thereon. A relatively deep polysilicon filled trench (26) is disposed in the epitaxial layer and substrate structure, the deep trench (26) having a composite oxide/nitride insulation layer (24) over its vertical and horizontal surfaces to provide a storage capacitor insulator. A relatively shallow trench is disposed in the epitaxial layer (36) over the deep trench (26) region, the shallow trench having an oxide insulation layer (46) on its vertical and horizontal surfaces thereof. A neck structure (34) of epitaxial polysilicon material extends from the top surface of the polysilicon filled deep trench (26) to the bottom surface of the shallow trench. Impurities are disposed in the epitaxial layer (36) on either side of the shallow trench to form semiconductor device drain (40) junctions and polysilicon material (48) is disposed in the shallow trench and over the epitaxial layer (36) to form semiconductor device transfer gate and wordline regions respectively.