公开(公告)号：DE68921599T2

公开(公告)日：1995-10-05

申请号：DE68921599

申请日：1989-12-08

Applicant: IBM

Inventor： DHONG SANG HOO ,  HWANG WEI NMI ,  LU NICKY CHUA-CHUN

IPC: G11C8/18 ,  G11C29/00 ,  G11C11/407 ,  G11C8/00 ,  G11C7/00 ,  H03K17/693

Abstract: A boost clock signal generator which provides a boost clock signal from a pair of phase clocks. A pair of differentially-connected FET transistors (46) which generate a boost clock signal. The transistors have drain connections connected to each of two clock signals, and commonly connected sources which form an output terminal for the boost clock signal. A series pass FET transistor (58, 59) is connected with each gate of the differential transistors for maintaining the gate at a floating voltage potential. A pair of capacitive elements couple the drain of each pair of differentially-connected FET transistors to the gate of an opposite transistor. A first and second logic circuit (78, 79) are connected to the series pass FET transistors for enabling one or the other of the differentially-connected FET transistors into conduction. The pair of capacitive coupling elements (51, 52) coupling the drain of each pair of differentially-connected FET transistors to the gate of an opposite transistor increase switching speed of the clock signal generator.

公开(公告)号：DE68921599D1

公开(公告)日：1995-04-13

申请号：DE68921599

申请日：1989-12-08

Applicant: IBM

Inventor： DHONG SANG HOO ,  HWANG WEI NMI ,  LU NICKY CHUA-CHUN

IPC: G11C8/18 ,  G11C29/00 ,  G11C11/407 ,  G11C8/00 ,  G11C7/00 ,  H03K17/693

Abstract: A boost clock signal generator which provides a boost clock signal from a pair of phase clocks. A pair of differentially-connected FET transistors (46) which generate a boost clock signal. The transistors have drain connections connected to each of two clock signals, and commonly connected sources which form an output terminal for the boost clock signal. A series pass FET transistor (58, 59) is connected with each gate of the differential transistors for maintaining the gate at a floating voltage potential. A pair of capacitive elements couple the drain of each pair of differentially-connected FET transistors to the gate of an opposite transistor. A first and second logic circuit (78, 79) are connected to the series pass FET transistors for enabling one or the other of the differentially-connected FET transistors into conduction. The pair of capacitive coupling elements (51, 52) coupling the drain of each pair of differentially-connected FET transistors to the gate of an opposite transistor increase switching speed of the clock signal generator.