公开(公告)号：DE2422123A1

公开(公告)日：1975-01-30

申请号：DE2422123

申请日：1974-05-08

Applicant: IBM

Inventor： CHU WILLIAM MAN-SIEW ,  LEE JAMES MINDA ,  LUCKETT GARY CLAIR

IPC: H03K3/356 ,  H03K3/286 ,  H03K17/60

公开(公告)号：DE68918203D1

公开(公告)日：1994-10-20

申请号：DE68918203

申请日：1989-07-27

Applicant: IBM

Inventor： CORREALE ANTHONY ,  LUCKETT GARY CLAIR

IPC: G06F1/26 ,  G05F3/24 ,  H01L21/822 ,  H01L21/8244 ,  H01L27/04 ,  H01L27/11 ,  H03K17/14 ,  H03K19/0185 ,  H03K19/0948

Abstract: A bias voltage generator for providing a voltage to bias static CMOS circuits, comprises a first compensation circuit arrangement (14) coupled to a power supply (+VDD) and a control node, the arrangement serving to generate at the control node a control voltage signal which compensates for tolerances in the power supply and device process parameters. A second compensation circuit arrangement (16) is coupled to the control node and serves to adjust the control voltage signal at the control node to compensate for device threshold voltage variations. The control voltage signal is inverted by an inverter circuit (18) to produce the output voltage of the generator. The bias voltage generator is incorporated with the static CMOS circuits on a very large scale integration chip.

公开(公告)号：DE68918203T2

公开(公告)日：1995-03-30

申请号：DE68918203

申请日：1989-07-27

Applicant: IBM

Inventor： CORREALE ANTHONY ,  LUCKETT GARY CLAIR

IPC: G06F1/26 ,  G05F3/24 ,  H01L21/822 ,  H01L21/8244 ,  H01L27/04 ,  H01L27/11 ,  H03K17/14 ,  H03K19/0185 ,  H03K19/0948

Abstract: A bias voltage generator for providing a voltage to bias static CMOS circuits, comprises a first compensation circuit arrangement (14) coupled to a power supply (+VDD) and a control node, the arrangement serving to generate at the control node a control voltage signal which compensates for tolerances in the power supply and device process parameters. A second compensation circuit arrangement (16) is coupled to the control node and serves to adjust the control voltage signal at the control node to compensate for device threshold voltage variations. The control voltage signal is inverted by an inverter circuit (18) to produce the output voltage of the generator. The bias voltage generator is incorporated with the static CMOS circuits on a very large scale integration chip.

公开(公告)号：DE2301855A1

公开(公告)日：1973-08-16

申请号：DE2301855

申请日：1973-01-15

Applicant: IBM

Inventor： LUCKETT GARY CLAIR ,  SONODA GEORGE

IPC: H03K19/0185 ,  H03K5/00