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    CIRCUITS AND METHODS FOR MULTIPLE CONTROL DATA PROCESSING SYSTEMS
    1.
    发明专利
    CIRCUITS AND METHODS FOR MULTIPLE CONTROL DATA PROCESSING SYSTEMS 未知

    公开(公告)号：CA1102425A

    公开(公告)日：1981-06-02

    申请号：CA320694

    申请日：1979-02-01

    Applicant: IBM

    Inventor： LUIZ FERNANDO A

    IPC: G06F13/14 ,  G06F3/06 ,  G06F9/46 ,  G06F9/52 ,  G06F12/00 ,  G06F13/12 ,  G06F15/16 ,  G06F15/17 ,  G06F15/177 ,  G06F3/04

    Abstract: CIRCUITS AND METHODS FOR MULTIPLE CONTROL IN DATA PROCESSING SYSTEMS In a data processing system in which two or more asynchronous processors operating as masters interchange requests and responses with a control unit that in turn controls a number of peripheral devices and operates as a slave to the processors, repetitive requests from a high speed processor can give rise to an impasse condition in which the control unit is blocked from completing the previously initiated sequence between a peripheral device and another processor. In accordance with the invention, the interface between the processors and the peripheral devices incorporates means which detect an uninterrupted sequence, of predetermined length, of busy responses from the control unit. If such responses are not interrupted by other actions, the system temporarily exercises independent control, returning a busy signal to the processors while enabling the control unit to ascertain whether reconnection to a specific processor is needed as the next step in a previously initiated processor program. If so, the control unit is enabled within the predetermined interval to effect the reconnection, either within the allotted time or on a succeeding repetition of the cycle. The exercise of a limited initiative for a predetermined time interval does not alter the basic master-slave relationship or unduly delay data transfer operations.

    DATA STORAGE TRACK PADDING APPARATUS
    4.
    发明专利
    DATA STORAGE TRACK PADDING APPARATUS 未知

    公开(公告)号：CA1052904A

    公开(公告)日：1979-04-17

    申请号：CA195196

    申请日：1974-03-18

    Applicant: IBM

    Inventor： LUIZ FERNANDO A

    IPC: G06F3/06 ,  G06F13/12 ,  G11B20/10 ,  G11B5/00 ,  G11B27/10

    Abstract: DATA STORAGE TRACK PADDING APPARATUS In data processing systems, several data storage files, such as disk files, are operated by a single, shared control unit for conducting normal read/write functions. Apparatus is located at and provided for each of the data storage files to assume control of the writing function from the control unit to pad a track with null characters from the end of the last record to a predetermined point on the track sensed by the file. The apparatus includes a local oscillator and apparatus for supplying the padding bits signals from the oscillator beginning with the termination of the control unit write gate signal for the track and continuing until a predetermined point of the track is detected. Apparatus is also provided for signaling the control unit that padding by the device is in progress and for signalling the control unit prior to the predetermined point.

    METHOD AND MEANS FOR PATH INDEPENDENT DEVICE RESERVATION AND RECONNECTION IN A MULTI-CPU AND SHARED DEVICE ACCESS SYSTEM
    5.
    发明专利
    METHOD AND MEANS FOR PATH INDEPENDENT DEVICE RESERVATION AND RECONNECTION IN A MULTI-CPU AND SHARED DEVICE ACCESS SYSTEM 未知

    公开(公告)号：CA1116260A

    公开(公告)日：1982-01-12

    申请号：CA324199

    申请日：1979-03-23

    Applicant: IBM

    Inventor： LUIZ FERNANDO A ,  SNYDER HARLAN C ,  SORG JOHN H JR

    IPC: G06F11/14 ,  G06F11/20 ,  G06F13/12 ,  G06F13/14 ,  G06F13/40 ,  G06F15/16 ,  G06F15/167 ,  G06F15/177 ,  G06F13/04

    Abstract: A METHOD AND MEANS FOR PATH INDEPENDENT DEVICE RESERVATION AND RECONNECTION IN A MULTI-CPU AND SHARED DEVICE ACCESS SYSTEM The A method and means for path independent reservation and reconnection of devices to CPU's operating in a multi-CPU and shared device access system environment. The multi-CPU and shared device access system comprises a plurality of sets of fan out paths (channels), each set coupling a corresponding CPU as a source node; a plurality of input/output devices; and a plurality of control nodes (control units), each node including means for accessing the devices, for selectively intercepting the paths in order to complete a signal path connection to a single destination device. Each control node further includes means(FIG. 2, element 25') for storing a table of independent path sets of CPU's and reserved devices and means(FIGS. 2-5) for managing the connection of CPU's to devices such that for any given selection, reservation or reconnection indication, the table is accessed by at least one control node for ascertaining whether the CPU is a member of a set of interfaces to which the device is reserved, if so, an available path is selected. The control nodes thus allocate dynamically dissimilar path sets to devices and CPU's on an allegiance basis in order to increase the signal path connection probability by the devices to counterpart CPU's involved in the reservation, release, or reconnection of the device and the CPU. SA9-77-043

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