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    Command retry control by peripheral devices
    2.
    发明授权
    Command retry control by peripheral devices 失效
    外围设备的命令重试控制

    公开(公告)号：US3688274A

    公开(公告)日：1972-08-29

    申请号：US3688274D

    申请日：1970-12-23

    Applicant: IBM

    Inventor： CORMIER ROGER L ,  SORG JOHN H JR ,  THORN CARYL A

    IPC: G06F11/14 ,  G06F13/00 ,  G06F13/12 ,  G06F3/04

    CPC classification number: G06F11/141 ,  G06F13/122 ,  G06F13/126

    Abstract: An input/output subsystem in which a peripheral device controller controls the device in response to commands received from an input/output (I/O) channel. A sequence of channel command words (CCWs) are stored in sequential addresses in a main memory. Some CCWs contain commands, other CCWs contain memory addresses for data but no commands. An initial instruction to the channel gives the channel the address where the first CCW is stored in the memory. The location address of the last CCW in the sequence containing a command is retained in a back-up register in the channel. Further CCWs are chained to the CCW containing the command to provide scattered addresses the the memory for the storage of blocks of data. At the completion of the data transfer operation associated with a CCW, the location address of the CCW is incremented by one address to thereby specify the next sequential address and hence, the next CCW. The next CCW contains an address at which further data are to be stored. The occurrence of a signal from the I/O device indicating an error or a nonerror condition, either of which conditions require the retrying of the original command, causes the channel to utilize the retained address to fetch the control work containing the command. This provides a way of backing up in the channel program without interrupting the computer to retry the original initializing command even though intervening control words were executed.

    Abstract translation: 输入/输出子系统，其中外围设备控制器响应于从输入/输出（I / O）通道接收的命令来控制设备。 信道命令字序列（CCW）存储在主存储器中的顺序地址中。 一些CCW包含命令，其他CCW包含数据的内存地址，但没有命令。 通道的初始指令给出通道第一个CCW存储在存储器中的地址。 包含命令的序列中最后一个CCW的位置地址保留在通道中的备份寄存器中。 进一步的CCW被链接到CCW，其中包含提供用于存储数据块的存储器的分散地址的命令。 在与CCW相关联的数据传送操作完成时，CCW的位置地址增加一个地址，从而指定下一个顺序地址，因此指定下一个CCW。 下一个CCW包含要存储更多数据的地址。 来自I / O设备的信号的出现指示错误或非错误状态，其中任一条件要求重试原始命令，使得该通道利用保留的地址来获取包含该命令的控制工作。 这提供了在通道程序中备份的方式，而不会中断计算机重试初始化初始化命令，即使执行了中间的控制字。

    METHOD AND MEANS FOR PATH INDEPENDENT DEVICE RESERVATION AND RECONNECTION IN A MULTI-CPU AND SHARED DEVICE ACCESS SYSTEM
    5.
    发明专利
    METHOD AND MEANS FOR PATH INDEPENDENT DEVICE RESERVATION AND RECONNECTION IN A MULTI-CPU AND SHARED DEVICE ACCESS SYSTEM 未知

    公开(公告)号：CA1116260A

    公开(公告)日：1982-01-12

    申请号：CA324199

    申请日：1979-03-23

    Applicant: IBM

    Inventor： LUIZ FERNANDO A ,  SNYDER HARLAN C ,  SORG JOHN H JR

    IPC: G06F11/14 ,  G06F11/20 ,  G06F13/12 ,  G06F13/14 ,  G06F13/40 ,  G06F15/16 ,  G06F15/167 ,  G06F15/177 ,  G06F13/04

    Abstract: A METHOD AND MEANS FOR PATH INDEPENDENT DEVICE RESERVATION AND RECONNECTION IN A MULTI-CPU AND SHARED DEVICE ACCESS SYSTEM The A method and means for path independent reservation and reconnection of devices to CPU's operating in a multi-CPU and shared device access system environment. The multi-CPU and shared device access system comprises a plurality of sets of fan out paths (channels), each set coupling a corresponding CPU as a source node; a plurality of input/output devices; and a plurality of control nodes (control units), each node including means for accessing the devices, for selectively intercepting the paths in order to complete a signal path connection to a single destination device. Each control node further includes means(FIG. 2, element 25') for storing a table of independent path sets of CPU's and reserved devices and means(FIGS. 2-5) for managing the connection of CPU's to devices such that for any given selection, reservation or reconnection indication, the table is accessed by at least one control node for ascertaining whether the CPU is a member of a set of interfaces to which the device is reserved, if so, an available path is selected. The control nodes thus allocate dynamically dissimilar path sets to devices and CPU's on an allegiance basis in order to increase the signal path connection probability by the devices to counterpart CPU's involved in the reservation, release, or reconnection of the device and the CPU. SA9-77-043

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