公开(公告)号：DE69004932T2

公开(公告)日：1994-05-19

申请号：DE69004932

申请日：1990-06-01

Applicant: IBM

Inventor： KERBAUGH MICHAEL L ,  KOBURGER III CHARLES W ,  MACHESNEY BRIAN J

IPC: H01L21/76 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/762

Abstract: A method of forming a planarized dielectric filled wide shallow trench (14) in a semiconductor substrate (10) is provided. A layer of etch stop (12) such as Si3N4 is deposited onto the semiconductor substrate (10), and wide trenches (14) are formed through the Si3N4 into the substrate (10) by conventional RIE. The surface of the substrate (10) including the trenches (14) have formed thereon a SiO2 coating (18), conforming to the surface of the substrate (10). A layer of etch resistant material (20) such as polysilicon is deposited onto the SiO2 material (18). The polysilicon (20) outside the width of the trenches (14) is then removed by chemical-mechanical polishing to expose the SiO2 there below, while leaving the SiO2 above the trenches (14) covered with polysilicon (20). The exposed SiO2 is then RIE etched down to the Si , leaving a plug of SiO2 capped with the etch resistant polysilicon (20) over each trench (14). These plugs are then removed by mechanical polishing down to the Si3N4, to provide a planarized upper surface of SiO2 and Si on the top of the substrate (10). The invention also is useful in forming planarized surfaces on substrates (10) having trenches (14) filled with conductive material.

公开(公告)号：DE69004932D1

公开(公告)日：1994-01-13

申请号：DE69004932

申请日：1990-06-01

Applicant: IBM

Inventor： KERBAUGH MICHAEL L ,  KOBURGER III CHARLES W ,  MACHESNEY BRIAN J

IPC: H01L21/76 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/762

Abstract: A method of forming a planarized dielectric filled wide shallow trench (14) in a semiconductor substrate (10) is provided. A layer of etch stop (12) such as Si3N4 is deposited onto the semiconductor substrate (10), and wide trenches (14) are formed through the Si3N4 into the substrate (10) by conventional RIE. The surface of the substrate (10) including the trenches (14) have formed thereon a SiO2 coating (18), conforming to the surface of the substrate (10). A layer of etch resistant material (20) such as polysilicon is deposited onto the SiO2 material (18). The polysilicon (20) outside the width of the trenches (14) is then removed by chemical-mechanical polishing to expose the SiO2 there below, while leaving the SiO2 above the trenches (14) covered with polysilicon (20). The exposed SiO2 is then RIE etched down to the Si , leaving a plug of SiO2 capped with the etch resistant polysilicon (20) over each trench (14). These plugs are then removed by mechanical polishing down to the Si3N4, to provide a planarized upper surface of SiO2 and Si on the top of the substrate (10). The invention also is useful in forming planarized surfaces on substrates (10) having trenches (14) filled with conductive material.

公开(公告)号：CA1244559A

公开(公告)日：1988-11-08

申请号：CA547694

申请日：1987-09-24

Applicant: IBM

Inventor： LU NICKY C-C ,  MACHESNEY BRIAN J

IPC: H01L27/04 ,  G11C11/24 ,  H01L21/20 ,  H01L21/205 ,  H01L21/74 ,  H01L21/763 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L21/465

Abstract: A FABRICATION METHOD FOR FORMING A SELF-ALIGNED CONTACT WINDOW AND CONNECTION IN AN EPITAXIAL LAYER AND DEVICE STRUCTURES EMPLOYING THE METHOD A fabrication process for providing an epitaxial layer on a silicon substrate and over predefined insulator-capped islands which forms a self-aligned contact window in the epitaxial layer. Application of the method to a three-dimensional dynamic random access memory (DRAM) device structure is shown, with an access transistor formed in monocrystalline silicon stacked on top of a trench capacitor. A fabrication method therefor is shown wherein the contact window for the source-to-trench connection is formed by self-aligned lateral epitaxial growth, followed by a contact-connection formation step using either a second epitaxial growth or a CVD refill and strapping process. The invention can be further applied to other device structures using the described principles, and more specifically to an inverter structure having the driver device stacked over the load-resistor as another example, which can be used as a basic building circuit unit for logic circuits and static-RAM cell.