公开(公告)号：CA2000995C

公开(公告)日：1994-11-08

申请号：CA2000995

申请日：1989-10-20

Applicant: IBM

Inventor： DHONG SANG H ,  HWANG WEI ,  LU NICKY C-C

IPC: G11C11/407 ,  G11C11/408 ,  H03K5/02 ,  H03K6/02 ,  H03K19/096

Abstract: Two embodiments of a wordline boost clock circuit that can be used in high speed DRAM circuits are disclosed. The clock circuits require only one boost capacitor and discharge the wordlines faster, improving the DRAM access time. The basic feature of the clock circuit is in the floating gate structure of the nmos device which drives the load to negative during the boosting. In the first embodiment of the clock, the gate of a first device is connected to a first node through a second device. A second node, connected to a wordline, is discharged through the first and a third device when a third node is high with a fourth node low. After a sufficient discharge of the second node, the fourth node is pulled to VDD turning the second device on and a fourth device off. The first (NMOS) transistor has its gate and drain connected together and forms a diode. When a boost capacitor pulls the third node down to negative, the first device stays completely off because of its diode configuration and the second node is pulled to negative through the third device. In the second embodiment, a first device is connected between a boost capacitor and a second node. The load is discharged through a third device with a fourth device on but a first and second device off. After a sufficient discharge of the load, a fourth device is turned off but a second device is turned on, making the third device a diode. When a fifth node is pulled to ground, the second node is pulled down to negative with the first device on. In the second embodiment circuit, the load discharges through only one nmos device and consequently discharges faster than the circuit of the first embodiment.

公开(公告)号：CA1314991C

公开(公告)日：1993-03-23

申请号：CA600744

申请日：1989-05-25

Applicant: IBM

Inventor： DHONG SANG H ,  LU NICKY C-C ,  HENKELS WALTER H

IPC: G11C11/405 ,  G11C11/404 ,  G11C11/409 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/06 ,  H01L27/092 ,  H01L27/108 ,  G11C11/24

Abstract: YO987-103 COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR TRANSISTOR AND ONE-CAPACITOR DYNAMIC-RANDOM-ACCESS MEMORY CELL AND FABRICATION PROCESS THEREFOR A complementary MOS one-capacitor dynamic RAM cell which operates with a non-boosted wordline without a threshold loss problem and which includes one storage capacitor and n- and p-type transfer devices connected to the storage capacitor which function as two complementary transistor devices having gates controlled by complementary signals on the RAM wordlines.

公开(公告)号：CA1289266C

公开(公告)日：1991-09-17

申请号：CA571409

申请日：1988-07-07

Applicant: IBM

Inventor： HWANG WEI ,  LU NICKY C-C

IPC: H01L27/10 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108 ,  H01L29/78 ,  H01L21/82 ,  H01L21/205

Abstract: Y09-87-022 VERTICAL TRENCH TRANSISTOR/CAPACITOR MEMORY CELL A new high density vertical trench transistor and trench capacitor DRAM (dynamic-random-access memory) cell is described incorporating a wafer with a semiconductor substrate and an epitaxial layer thereon including a vertical transistor disposed in a shallow trench stacked above and self-aligned with a capacitor in a deep trench. The stacked vertical transistor 14 has a channel partly on the horizontal surface and partly along the shallow trench sidewalls. The drain of the access transistor is a lightly-doped drain structure connected to a bitline element. The source of the transistor, located at the bottom of the transistor trench and on top of the center of the trench capacitor, is self-aligned and connected to polysilicon contained inside the trench capacitor. Three sidewalls or the access transistor are surrounded by thick oxide isolation and the remaining one side is connected to drain and bitline contacts. The memory cell is located inside an n-well and uses the n-well and heavily-doped substrate as the capacitor counter-electrode plate. The cell storage node is the polysilicon inside the trench capacitor and include steps for growing epitaxial layers wherein an opening is left which serves as the shallow trench access transistor region and provides self-alignment with the deep trench storage capacitor.

公开(公告)号：CA1285333C

公开(公告)日：1991-06-25

申请号：CA570365

申请日：1988-06-24

Applicant: IBM

Inventor： HWANG WEI ,  LU NICKY C-C

IPC: H01L27/04 ,  H01L21/334 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/94 ,  H01L21/82

Abstract: Y0987-020 HIGH DENSITY VERTICAL TRENCH TRANSISTOR AND CAPACITOR MEMORY CELL STRUCTURE AND FABRICATICN METHOD THEREFOR A semiconductor memory cell structure incorporating a vertical access transistor over a trench storage capacitor including a semiconductor wafer having a semiconductor substrate and an epitaxial layer d1sposed thereon. A relatively deep polysilicon filled trench is disposed in the epitaxial layer and substrate structure, the deep trench having a composite oxide/nitride insulation layer over its vertical and horizontal surfaces to provide a storage capacitor lnsulator. A relatively shallow trench is disposed in the epitaxial layer over the deep trench region, the shallow trench having an oxide insulation layer on its vertical and horizontal surfaces thereof. A neck structure of epitaxial polysilicon material extends from the top surface of the polysilicon filled deep trench to the bottom surface of the shallow trench. Impurities are disposed in the epitaxial layer on either side of the shallow trench to form semiconductor device drain junctions and polysilicon material is disposed in the shallow trench and over the epitaxial layer to form semiconductor device transfer gate and wordline regions respectively.

公开(公告)号：CA2006745C

公开(公告)日：1993-06-15

申请号：CA2006745

申请日：1989-12-27

Applicant: IBM

Inventor： DHONG SANG H ,  HWANG WEI ,  LU NICKY C-C

IPC: H01L21/223 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/108 ,  H01L27/112 ,  H01L29/78 ,  H01L29/76 ,  H01L29/784

Abstract: A CROSS-POINT LIGHTLY-DOPED DRAIN-SOURCE TRENCH TRANSISTOR AND FABRICATION PROCESS THEREFOR A structure and fabrication process for a self-aligned, lightly-doped drain/source n-channel field-effect transistor wherein a trench is formed in a well region in a wafer including an epitaxial layer on a substrate. A first, heavily doped drain region and bit line element is formed around the trench on the surface of the well, and a second, lightly-doped drain region is formed proximate to the first drain region and self-aligned to the trench sidewalls. A source region is located beneath the trench, which is filled with polysilicon, above which is gate and further polysilicon forming a transfer wordline. The well region at the trench sidewalls are doped to control the device threshold level, and the device is thereby also located at a wordline/bitline cross-point.

公开(公告)号：CA2006745A1

公开(公告)日：1990-11-22

申请号：CA2006745

申请日：1989-12-27

Applicant: IBM

Inventor： DHONG SANG H ,  HWANG WEI ,  LU NICKY C-C

IPC: H01L21/223 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/108 ,  H01L27/112 ,  H01L29/78

Abstract: A structure and fabrication process for a self-aligned, lightly-doped drain/source n-channel field-effect transistor wherein a trench is formed in a well region (15) in a wafer including an epitaxial layer (12) on a substrate (10). A first, heavily doped drain region and bit line element (18) is formed around the trench on the surface of the well (15) , and a second, lightly-doped drain region (24) is formed proximate to the first drain region (18) and self-aligned to the trench sidewalls. A source region (26) is located beneath the trench, which is filled with polysilicon (32), above which is gate and further polysilicon forming a transfer wordline (33). The gate polysilicon (32) is separated from the trench side walls by a layer (30) of gate oxide insulation. The well region (15) at the trench sidewalls are doped to control the device threshold level, and the device is thereby also located at a wordline/bitline cross-point.

公开(公告)号：CA1244559A

公开(公告)日：1988-11-08

申请号：CA547694

申请日：1987-09-24

Applicant: IBM

Inventor： LU NICKY C-C ,  MACHESNEY BRIAN J

IPC: H01L27/04 ,  G11C11/24 ,  H01L21/20 ,  H01L21/205 ,  H01L21/74 ,  H01L21/763 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L21/465

Abstract: A FABRICATION METHOD FOR FORMING A SELF-ALIGNED CONTACT WINDOW AND CONNECTION IN AN EPITAXIAL LAYER AND DEVICE STRUCTURES EMPLOYING THE METHOD A fabrication process for providing an epitaxial layer on a silicon substrate and over predefined insulator-capped islands which forms a self-aligned contact window in the epitaxial layer. Application of the method to a three-dimensional dynamic random access memory (DRAM) device structure is shown, with an access transistor formed in monocrystalline silicon stacked on top of a trench capacitor. A fabrication method therefor is shown wherein the contact window for the source-to-trench connection is formed by self-aligned lateral epitaxial growth, followed by a contact-connection formation step using either a second epitaxial growth or a CVD refill and strapping process. The invention can be further applied to other device structures using the described principles, and more specifically to an inverter structure having the driver device stacked over the load-resistor as another example, which can be used as a basic building circuit unit for logic circuits and static-RAM cell.