公开(公告)号：EP1815522A4

公开(公告)日：2010-11-10

申请号：EP05851962

申请日：2005-11-21

Applicant: IBM

Inventor： KOTHANDARAMAN CHANDRASEKHARAN ,  MACIEJEWSKI EDWARD

IPC: H01L23/525

CPC classification number: H01L23/5256 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：WO2006057980A2

公开(公告)日：2006-06-01

申请号：PCT/US2005042212

申请日：2005-11-21

Applicant: IBM ,  KOTHANDARAMAN CHANDRASEKHARAN ,  MACIEJEWSKI EDWARD

Inventor： KOTHANDARAMAN CHANDRASEKHARAN ,  MACIEJEWSKI EDWARD

IPC: H01L29/00

CPC classification number: H01L23/5256 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A fuse structure and method of forming the same is described, wherein the conductive body (50) of the fuse is formed from a crystalline semiconductor body (52) on an insulator (53), preferably of a silicon-on-insulator wafer, surrounded by a fill-in dielectric (54). The fill-in dielectric (54) is preferably a material that minimizes stresses on the crystalline body (52), such as an oxide. The crystalline semiconductor body (52) may be doped. The conductive body (50) may also include a conductive layer (51), such as a silicide layer, on the upper surface of the crystalline semiconductor body (52). This fuse structure may be successfully programmed over a wide range of programming voltages and time.

Abstract translation: 描述了一种熔丝结构及其形成方法，其中，熔丝的导电体（50）由绝缘体（53）上的晶体半导体本体（52）形成，绝缘体（53） 通过填充电介质（54）。 填充电介质（54）优选是使结晶体（52）上的应力最小化的材料，例如氧化物。 晶体半导体本体（52）可以被掺杂。 导电体（50）还可以包括在晶体半导体本体（52）的上表面上的诸如硅化物层的导电层（51）。 这种熔丝结构可以在广泛的编程电压和时间范围内成功编程。