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    Programmable fuse device
    3.
    发明专利
    Programmable fuse device 有权

    公开(公告)号：JP2004111959A

    公开(公告)日：2004-04-08

    申请号：JP2003310674

    申请日：2003-09-02

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： KOTHANDARAMAN CHANDRASEKHARAN ,  S SUNDAR KUMAR

    IPC: H01L21/82 ,  G11C17/18

    CPC classification number: G11C17/18

    Abstract: PROBLEM TO BE SOLVED: To obtain technical advantages as a device, system, and method of programming an electric fuse by using a transistor to which an active well bias is imparted.
    SOLUTION: In contrast to being grounded, a transistor (i.e. MOSFET) 33 operates through a well bias to program an electric fuse 31. With respect to the programming transistor operated by the active well bias, the fuse 31 can be programmed by the larger energy than that in the case of utilizing in the well with the transistor of the same size grounded. Thus, the smaller transistor can be used for programming the fuse 31. In the enforcement of a plurality of fuses, the programming transistor can be arranged in the same "well" in such a state that the common independent V
    bias is imparted to the entire well through a body controlling circuit 37, while programming the selected fuse 31.
    COPYRIGHT: (C)2004,JPO

    Electrically programmable fuse using anisometric contact and fabrication method
    5.
    发明专利
    Electrically programmable fuse using anisometric contact and fabrication method 审中-公开
    电气可编程保险丝使用异构接触和制造方法

    公开(公告)号：JP2011009745A

    公开(公告)日：2011-01-13

    申请号：JP2010142058

    申请日：2010-06-22

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： KOTHANDARAMAN CHANDRASEKHARAN ,  MOY DAN ,  JOHN MATTHEW SAFRAN ,  NORMAN WHITELAW ROBSON

    IPC: H01L21/82

    CPC classification number: H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: PROBLEM TO BE SOLVED: To provide an electrically programmable fuse including anisometric contacts having improved thermal characteristics, and to provide a fabrication method thereof.SOLUTION: The electrically programmable fuse includes: an anode contact region 110 and a cathode contact region 118 formed of a polysilicon layer having a silicide layer formed thereon; a fuse link 116 which conductively connects the cathode contact region with the anode contact region and is programmable by applying a programming current; and a plurality of anisometric contacts 120 formed on the silicide layer of the cathode contact region or on both silicide layers of the cathode contact region and the anode contact region in a predetermined configuration, respectively.

    Abstract translation: 要解决的问题：提供一种电可编程保险丝，其包括具有改进的热特性的不等尺寸触点，并提供其制造方法。解决方案：电可编程熔丝包括：阳极接触区域110和由多晶硅形成的阴极接触区域118 层，其上形成有硅化物层; 熔丝连接器116，其将阴极接触区域与阳极接触区域导电连接，并通过应用编程电流进行编程; 以及分别形成在阴极接触区域的硅化物层上或在阴极接触区域和阳极接触区域的两个硅化物层上形成预定结构的多个不规则接触件120。

    FUSE LINK
    6.
    发明申请
    FUSE LINK 审中-公开

    公开(公告)号：WO0193331A3

    公开(公告)日：2002-07-18

    申请号：PCT/US0115998

    申请日：2001-05-18

    Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

    Inventor： KOTHANDARAMAN CHANDRASEKHARAN ,  GRELLNER FRANK ,  IYER SUNDAR UMAR

    IPC: H01L21/82 ,  H01L23/525

    CPC classification number: H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Described herein is a fuse incorporating a covering layer disposed on a conductive layer, which is disposed on a polysilicon layer. The covering layer preferably comprises a relatively inert material, such as a nitride etchant barrier. The covering layer preferably has a region of relatively less-inert filler material. Upon programming of the fuse, the conductive layer, which can be a silicide, preferentially degrades in the region underlying the filler material of the covering layer. This preferential degradation results in a predictable "blowing" of the fuse in the fuse region underlying the filler material. Since the "blow" area is predictable, damage to adjacent structures can be minimized or eliminated.

    Abstract translation: 这里描述的是一种保险丝，其包括设置在多晶硅层上的导电层上的覆盖层。 覆盖层优选地包括相对惰性的材料，例如氮化物蚀刻剂屏障。 覆盖层优选具有相对较少惰性填料的区域。 在对熔丝进行编程时，可以是硅化物的导电层优选在覆盖层的填充材料下方的区域中降解。 这种优先的劣化导致在填充材料下面的保险丝区域中的可预见的“熔断”熔丝。 由于“打击”区域是可预测的，所以可以最小化或消除对相邻结构的损坏。

    Rippen-Antisicherung mit verringerter Programmierspannung und Verfahren zu deren Herstellung
    8.
    发明专利
    Rippen-Antisicherung mit verringerter Programmierspannung und Verfahren zu deren Herstellung 未知

    公开(公告)号：DE112010003252B4

    公开(公告)日：2015-12-03

    申请号：DE112010003252

    申请日：2010-08-04

    Applicant: IBM

    Inventor： KOTHANDARAMAN CHANDRASEKHARAN ,  CHENG KANGGUO ,  BOOTH JR ROGER A

    IPC: H01L23/525 ,  H01L21/768

    Abstract: Struktur einer Antisicherung, die Folgendes umfasst: ein Substrat (100); eine Vielzahl paralleler leitender Rippen (104), die auf dem Substrat angeordnet sind, wobei jede der Rippen ein erstes Ende (108) und ein zweites Ende (106) aufweist; einen Isolator (120), der das erste Ende der Rippen bedeckt; einen ersten elektrischen Leiter (140), der auf dem Isolator angeordnet ist, wobei der erste elektrische Leiter durch den Isolator vom ersten Ende der Rippen elektrisch isoliert ist; und einen zweiten elektrischen Leiter (180), der mit dem zweiten Ende der Rippen elektrisch verbunden ist, wobei der Isolator eine Dicke aufweist, die ausreicht, um beim Anlegen einer vorgegebenen Spannung zwischen dem zweiten elektrischen Leiter und dem ersten elektrischen Leiter durchzubrechen und dadurch über die Rippen eine ständige elektrische Verbindung zwischen dem zweiten elektrischen Leiter und dem ersten elektrischen Leiter zu bilden.

    FIN ANTI-FUSE WITH REDUCED PROGRAMMING VOLTAGE
    9.
    发明申请
    FIN ANTI-FUSE WITH REDUCED PROGRAMMING VOLTAGE 审中-公开
    具有减少编程电压的FIN防冻保护

    公开(公告)号：WO2011019562A2

    公开(公告)日：2011-02-17

    申请号：PCT/US2010044385

    申请日：2010-08-04

    Applicant: IBM ,  BOOTH ROGER A ,  CHENG KANGGUO ,  KOTHANDARAMAN CHANDRASEKHARAN

    Inventor： BOOTH ROGER A ,  CHENG KANGGUO ,  KOTHANDARAMAN CHANDRASEKHARAN

    IPC: H01L23/62 ,  H01L21/82

    CPC classification number: H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method forms an anti-fuse structure comprises a plurality of parallel conductive fins positioned on a substrate, each of the fins has a first end and a second end. A second electrical conductor is electrically connected to the second end of the fins. An insulator covers the first end of the fins and a first electrical conductor is positioned on the insulator. The first electrical conductor is electrically insulated from the first end of the fins by the insulator. The insulator is formed to a thickness sufficient to break down on the application of a predetermined voltage between the second electrical conductor and the first electrical conductor and thereby form an uninterrupted electrical connection between the second electrical conductor and the first electrical conductor through the fins.

    Abstract translation: 一种形成抗熔丝结构的方法包括位于基板上的多个平行的导电翅片，每个翼片具有第一端和第二端。 第二电导体电连接到散热片的第二端。 绝缘体覆盖翅片的第一端并且第一电导体位于绝缘体上。 第一电导体通过绝缘体与散热片的第一端电绝缘。 绝缘体形成为足以在第二电导体和第一电导体之间施加预定电压时分解的厚度，从而通过翅片在第二电导体和第一电导体之间形成不间断的电连接。

    AN ELECTRICALLY PROGRAMMABLE FUSE FOR SILICON-ON-INSULATOR (SOI) TECHNOLOGY
    10.
    发明申请
    AN ELECTRICALLY PROGRAMMABLE FUSE FOR SILICON-ON-INSULATOR (SOI) TECHNOLOGY 审中-公开
    一种用于硅绝缘体（SOI）技术的电可编程保险丝

    公开(公告)号：WO2006057980A2

    公开(公告)日：2006-06-01

    申请号：PCT/US2005042212

    申请日：2005-11-21

    Applicant: IBM ,  KOTHANDARAMAN CHANDRASEKHARAN ,  MACIEJEWSKI EDWARD

    Inventor： KOTHANDARAMAN CHANDRASEKHARAN ,  MACIEJEWSKI EDWARD

    IPC: H01L29/00

    CPC classification number: H01L23/5256 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A fuse structure and method of forming the same is described, wherein the conductive body (50) of the fuse is formed from a crystalline semiconductor body (52) on an insulator (53), preferably of a silicon-on-insulator wafer, surrounded by a fill-in dielectric (54). The fill-in dielectric (54) is preferably a material that minimizes stresses on the crystalline body (52), such as an oxide. The crystalline semiconductor body (52) may be doped. The conductive body (50) may also include a conductive layer (51), such as a silicide layer, on the upper surface of the crystalline semiconductor body (52). This fuse structure may be successfully programmed over a wide range of programming voltages and time.

    Abstract translation: 描述了一种熔丝结构及其形成方法，其中，熔丝的导电体（50）由绝缘体（53）上的晶体半导体本体（52）形成，绝缘体（53） 通过填充电介质（54）。 填充电介质（54）优选是使结晶体（52）上的应力最小化的材料，例如氧化物。 晶体半导体本体（52）可以被掺杂。 导电体（50）还可以包括在晶体半导体本体（52）的上表面上的诸如硅化物层的导电层（51）。 这种熔丝结构可以在广泛的编程电压和时间范围内成功编程。

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