公开(公告)号：US3870900A

公开(公告)日：1975-03-11

申请号：US41505473

申请日：1973-11-12

Applicant: IBM

Inventor： MALAVIYA SHASHI D

IPC: H03D3/02 ,  H03D13/00 ,  H03K5/20

CPC classification number: H03D3/02 ,  H03D13/003

Abstract: A phase discriminator, for operation in a phase-locked loop, which is characterized by a virtually infinite capture range. The discriminator comprises circuit means responsive to the input data and clock pulses for generating a signal having a duration indicative of the phase difference between the pulses, a flipflop which identifies the phase relationship between the pulses, and a current switch circuit responsive to the flip-flop output for generating an output pulse having a potential level indicative of the phase relationship between the input pulses, and responsive to the circuit means for generating the output pulse for a duration proportional to the phase difference between them. The circuit is also capable of locking pulses of widely different frequencies and tolerates a large variation of input pulse widths.

Abstract translation: 相位鉴别器，用于在锁相环中操作，其特征在于几乎无限的捕获范围。 鉴频器包括响应于输入数据和时钟脉冲的电路装置，用于产生具有指示脉冲之间的相位差的持续时间的信号，识别脉冲之间的相位关系的触发器和响应于该脉冲的电流开关电路 触发器输出，用于产生具有指示输入脉冲之间的相位关系的电位电平的输出脉冲，并且响应于电路装置产生与它们之间的相位差成比例的持续时间的输出脉冲。 该电路还能够锁定宽频率不同的脉冲，并且可以承受大的输入脉冲宽度变化。

公开(公告)号：US3899753A

公开(公告)日：1975-08-12

申请号：US46694274

申请日：1974-05-06

Applicant: IBM

Inventor： MALAVIYA SHASHI D

IPC: H03K3/283 ,  H03B5/36

CPC classification number: H03K3/283

Abstract: A series-resonant crystal provides ac emitter coupling for a current switch whose output is fed back to its input to sustain oscillations at the resonant frequency of the crystal. A mixer circuit is provided so that the feedback is positive for small signal amplitudes whereby oscillations build up spontaneously when the circuit is switched on and then controls the feedback automatically so that it becomes negative for large signal amplitudes. This limits the output without resort to device saturation or cut-off, both of which adversely affect the speed, and as such, limit the high frequency performance of the oscillator.

Abstract translation: 串联谐振晶体为电流开关提供交流发射极耦合，其输出反馈到其输入以维持晶体谐振频率处的振荡。 提供混频器电路，使得对于小信号幅度的反馈是正的，由此当电路接通时振荡自发地建立，然后自动控制反馈，使得对于大信号幅度而言它变为负值。 这限制了输出，而不需要设备饱和或截止，这两者都对速度产生不利影响，因此限制了振荡器的高频性能。

公开(公告)号：JPS62105467A

公开(公告)日：1987-05-15

申请号：JP25710886

申请日：1986-10-30

Applicant: IBM

Inventor： GOTH GEORGE R ,  MALAVIYA SHASHI D

IPC: H01L27/04 ,  G11C11/403 ,  H01L21/762 ,  H01L21/822 ,  H01L21/8229 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/102 ,  H01L27/108

公开(公告)号：CA1128207A

公开(公告)日：1982-07-20

申请号：CA331674

申请日：1979-07-12

Applicant: IBM

Inventor： MALAVIYA SHASHI D

IPC: G11C11/416 ,  G11C17/06 ,  G11C17/08 ,  G11C11/40

Abstract: AN OPEN COLLECTOR BIT DRIVER/SENSE AMPLIFIER Disclosed is an improved sense amplifier/bit driver circuit including first and second transistors connected in a current mirror configuration. A bit line connected to a plurality of memory cells is connected to the collector of the first of the two transistors while the second of the transistors provides an output at its collector. A current source is connected to the base regions of both the first and second transistors for supplying current when a bit line is to be selected. Current flow through the second transistor is supplied to additional circuitry including a driver circuit, a clamping circuit and a zero filter circuit. Also disclosed is a reference voltage generator which accurately tracks the sense amplifier circuit and provides a reference voltage at or near the midpoint between a binary 1 and binay 0 level. The sense amplifier sustantially senses current rather than voltage and also acts as a high power over driven bit driver. FI9-78-051

公开(公告)号：FR2413814A1

公开(公告)日：1979-07-27

申请号：FR7834437

申请日：1978-11-30

Applicant: IBM

Inventor： MALAVIYA SHASHI D

IPC: H03L7/16 ,  H03L7/07 ,  H03L7/08 ,  H03L7/099 ,  H04L7/033 ,  H03B3/10 ,  H03B5/30

公开(公告)号：FR2279266A1

公开(公告)日：1976-02-13

申请号：FR7518146

申请日：1975-06-03

Applicant: IBM

Inventor： MALAVIYA SHASHI D

IPC: H03M1/54 ,  H03M1/00 ,  H03K13/08

公开(公告)号：CA970830A

公开(公告)日：1975-07-08

申请号：CA159877

申请日：1972-12-27

Applicant: IBM

Inventor： MALAVIYA SHASHI D

IPC: G01R31/26

Abstract: A first sinusoidal signal at a microwave frequency is applied to the input port of a transistor while simultaneously therewith a second sinusoidal signal at the same frequency is applied to the output port. The magnitude and phase of the signals are adjusted to effect successively short-circuit and open-circuit conditions at the input and output ports. For each condition the magnitudes and phases of the incident and reflected waves are measured or determined at the ports. These measurements may then be used to compute four of the usual transistor parameters and to check the self-consistency of the measurement. A second set of measurements may then be made at a different microwave frequency to compute additional transistor parameters. The beta of the transistor may be directly measured at either microwave frequency.

公开(公告)号：CA1258124A

公开(公告)日：1989-08-01

申请号：CA508350

申请日：1986-05-05

Applicant: IBM

Inventor： GOTH GEORGE R ,  MALAVIYA SHASHI D

IPC: H01L27/04 ,  G11C11/403 ,  H01L21/762 ,  H01L21/822 ,  H01L21/8229 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/102 ,  H01L27/108 ,  H01L21/82

Abstract: A high density integrated circuit structure, for example a dynamic memory cell, is described which includes an active/passive device in combination with a capacitor structure. The capacitor structure is of the polysilicon-oxide-silicon type and is formed on the sidewalls of a mesa-shaped and dielectrically isolated region of silicon material resulting from the formation of an isolation trench in the silicon. The trench is filled with a plastic material, such as polyimide. The capacitor is formed by the isolated region of silicon material which functions as the first capacitor plate, a doped polysilicon layer provided on the vertical walls of the mesa serving as the second capacitor plate and a thin dielectric layer interposed between the two plates serving as the capacitor's dielectric. Since the polysilicon is wrapped around the periphery of the mesa as a coating on the vertical sidewalls thereof, it gives rise to a large storage capacitance without an increase in the cell size.

公开(公告)号：BR8104010A

公开(公告)日：1982-03-16

申请号：BR8104010

申请日：1981-06-26

Applicant: IBM

Inventor： MAGDO INGRID E ,  GOTH GEORGE R ,  MALAVIYA SHASHI D

IPC: H01L21/3205 ,  H01L21/033 ,  H01L21/28 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/331 ,  H01L21/336 ,  H01L21/60 ,  H01L29/41 ,  H01L29/417 ,  H01L29/73 ,  H01L29/732 ,  H01L29/78 ,  H01L27/00

Abstract: A method for forming integrated circuits having a pattern of narrow dimensioned dielectric regions and, more particularly self-aligned metal process is described which achieves self-aligned metal to silicon contacts and sub-micron contact-to-contact and metal-to-metal spacing. The insulation between the contacts and the metal is a pattern of dielectric material having a thickness dimension in the order of a micron or less. The metal or dielectric structure is substantially planar. The method of forming integrated circuits with this structure involves providing a silicon body (50, 51) and then forming a first insulating layer (52) on a major surface of the silicon body. A layer of polycrystalline silicon (53) is formed thereover. Openings are made in the polycrystalline silicon layer by reactive ion etching which results in the structure having substantially horizontal surfaces and substantially vertical surfaces. A second insulating layer (55) is then formed on both the substantially horizontal surfaces and substantially vertical surfaces. Reactive ion etching of this second insulating layer substantially removes the horizontal layers and provides a narrow dimensioned dielectric pattern of regions (56) on the major surface of the silicon body (50). The remaining polycrystalline silicon layer (53) is then removed by etching to leave the narrow dimensioned regions (56) on the major surfaces of the silicon body. A conductive layer is blanket desposited over the narrow dimensioned regions and areas in between. A blanket layer of a plastic material over the conductive layer to planarize the surface is accomplished. Reactive ion etching the plastic material and the conductive layer is continued until the tops of the narrow dimensioned regions (56) are reached leaving the structure of patterns (59 to 64) of metal filling the regions between the pattern of dielectric material having a thickness dimension in the order of a micron or less.

公开(公告)号：DE2359997A1

公开(公告)日：1974-07-04

申请号：DE2359997

申请日：1973-12-01

Applicant: IBM

Inventor： MALAVIYA SHASHI D

IPC: H03K3/289 ,  H03K3/286

Abstract: A binary divider circuit of the master-slave type. The master bistable flip-flop and the slave bistable flip-flop are arranged in series between the voltage supply lines so that current flows from one of the supply lines through one of the bistable circuits and then through the other of the bistable circuits into the other supply line. The series arrangement of the bistable circuits provides reduced power dissipation and increased switching speed. The disclosed embodiment further comprises diodes extending from one voltage supply line to the master bistable circuit for bypassing current around the slave bistable circuit and to the master bistable circuit so as to provide higher output power and/or faster switching speed for the master bistable circuit. The diodes further function as a voltage regulator for maintaining the voltage across each bistable circuit approximately constant to prevent the bistable circuits from interacting with each other as their respective impedances vary during switching operations.