公开(公告)号：US3904454A

公开(公告)日：1975-09-09

申请号：US42788873

申请日：1973-12-26

Applicant: IBM

Inventor： MAGDO INGRID E ,  MAGDO STEVEN

IPC: H01L29/73 ,  H01L21/00 ,  H01L21/306 ,  H01L21/308 ,  H01L21/331 ,  H01L21/283 ,  H01L21/312 ,  H01L21/316

CPC classification number: H01L21/00 ,  H01L21/308 ,  Y10S148/043 ,  Y10S148/051 ,  Y10S148/113 ,  Y10S148/114 ,  Y10S438/947

Abstract: A method in the fabrication of integrated circuits for forming small openings through electrically insulative passivating layers on semiconductor surfaces. First and second layers of different insulative material are formed on the semiconductor surface. Then, a first slot extending through the second or top layer is formed by chemical etching through an etch-resistant mask with an etchant which selectively etches the material in the top layer. The top layer is then covered with a photoresist mask having a second slot which crosses the first slot, and the structure is subjected to chemical etching through the photoresist mask with an etchant that selectively etches the material in the first or bottom layer to, thereby, form a small opening through this bottom layer which is defined by the intersecting portions of the first and second slots.

Abstract translation: 制造用于通过半导体表面上的电绝缘钝化层形成小开口的集成电路的制造方法。 第一和第二层不同的绝缘材料形成在半导体表面上。 然后，延伸穿过第二或顶层的第一槽通过化学蚀刻通过具有选择性蚀刻顶层中的材料的蚀刻剂的耐蚀刻掩模形成。 然后用具有穿过第一槽的第二槽的光致抗蚀剂掩模覆盖顶层，并且用蚀刻剂对结构进行化学蚀刻，所述蚀刻剂选择性地蚀刻第一层或底层中的材料， 形成通过该第一槽和第二槽的相交部分限定的该底层的小开口。

公开(公告)号：US3918148A

公开(公告)日：1975-11-11

申请号：US46107874

申请日：1974-04-15

Applicant: IBM

Inventor： MAGDO INGRID E ,  MAGDO STEVEN

IPC: H05K3/46 ,  H01L21/48 ,  H01L21/768 ,  H01L23/14 ,  H01L23/498 ,  H01L23/522 ,  H01L23/538 ,  B01J17/00

CPC classification number: H01L23/538 ,  H01L21/4846 ,  H01L23/147 ,  H01L23/49894 ,  H01L2224/16225 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/14 ,  Y10T29/4913 ,  Y10T29/49144

Abstract: An integrated circuit chip carrier with multi-level metallurgy, in which the effects of the metallurgy in causing elevation irregularitiies at the various levels of the structure are minimized, is produced by a method wherein a first plurality of levels of metallization patterns respectively separated by layers of dielectric material are first formed on a planar primary layer supported on a temporary substrate having a chemical etchability different from that of the layer. The primary layer is electrically insulative with respect to said metallization patterns. Then, a supporting layer is formed on the uppermost covering layer, after which the substrate is removed with a chemical etchant which preferentially etches the substrate away from the insulative layer. Next, an opposite plurality of levels of metallization patterns are formed on the side of the insulative layer opposite to the first formed metallization patterns. These opposite metallization patterns are also respectively separated by covering layers of dielectric material.

Abstract translation: 一种具有多层次冶金的集成电路芯片载体，其中冶金技术在结构的各个层次上引起高程不规则性的效果最小化是通过一种方法产生的，其中第一多层次的金属化图案分别由层间隔开 介电材料首先形成在具有不同于该层的化学蚀刻性的临时衬底上的平面初级层上。 主层相对于所述金属化图案是电绝缘的。 然后，在最上层的覆盖层上形成支撑层，然后用化学蚀刻剂除去衬底，该蚀刻剂优先蚀刻衬底远离绝缘层。 接下来，在与第一形成的金属化图案相对的绝缘层的侧面上形成相反的多个级别的金属化图案。 这些相反的金属化图案也分别通过覆盖介电材料层分开。

公开(公告)号：US3894891A

公开(公告)日：1975-07-15

申请号：US47398974

申请日：1974-05-28

Applicant: IBM

Inventor： MAGDO INGRID E ,  MAGDO STEVEN

IPC: H01L21/762 ,  H01L27/00 ,  H01L29/00 ,  H01L7/34

CPC classification number: H01L27/00 ,  H01L21/76202 ,  H01L29/00 ,  Y10S148/085 ,  Y10S148/117 ,  Y10S148/122

Abstract: A space charge limited transistor formed on a high resistivity substrate of at least 10,000 ohm-centimeter silicon of one conductivity type. One surface of the substrate is provided with spaced recessed oxide regions. The alternate spaces between the oxide regions are occupied by impurity zones of said one conductivity type. The intervening alternate spaces between the oxide regions are occupied by impurity zones of the other conductivity type. The impurity concentrations of the aforesaid impurity zones are at least several orders of magnitude higher than that of the substrate where the zones are separated from each other by the aforesaid oxide regions. The dielectric relaxation time is much larger than the carrier transit time within the substrate below and between adjacent impurity zones of the same conductivity type.

Abstract translation: 形成在一个导电类型的至少10,000欧姆厘米硅的高电阻率衬底上的空间电荷限制晶体管。 衬底的一个表面设置有间隔开的凹陷氧化物区域。 氧化物区域之间的交替空间由所述一种导电类型的杂质区占据。 氧化物区域之间的中间交替空间由另一种导电类型的杂质区占据。 上述杂质区域的杂质浓度比通过上述氧化物区域彼此分离的基板的杂质浓度高出几个数量级。 电介质弛豫时间远大于相同导电类型的相邻杂质区之下和之间的衬底内的载流子传播时间。

公开(公告)号：US3900344A

公开(公告)日：1975-08-19

申请号：US34445573

申请日：1973-03-23

Applicant: IBM

Inventor： MAGDO INGRID E

IPC: H01L21/82 ,  H01L27/06 ,  H01L29/00 ,  B44D1/18 ,  H01L11/00

CPC classification number: H01L27/0664 ,  H01L21/82 ,  H01L29/00

Abstract: A novel Schottky Barrier structure which is integratable with standard integrated circuits comprising a metal layer of Al2Pt in contact with a high resistivity semiconductor region. The structure is fabricated by first forming a platinum silicide layer on said silicon substrate and then applying a metallic layer comprising aluminum on said first layer, after which the structure is sintered at a temperature of at least 400*C. for at least an hour.

公开(公告)号：US3861968A

公开(公告)日：1975-01-21

申请号：US26388172

申请日：1972-06-19

Applicant: IBM

Inventor： MAGDO INGRID E ,  MAGDO STEVEN

IPC: H01L29/73 ,  H01L21/22 ,  H01L21/32 ,  H01L21/331 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/082 ,  H01L29/78 ,  H01L7/36

CPC classification number: H01L21/76294 ,  H01L21/32 ,  H01L21/823878 ,  H01L27/0826 ,  Y10S148/026 ,  Y10S148/037 ,  Y10S148/053 ,  Y10S148/085 ,  Y10S148/117

Abstract: A method of fabricating a planar dielectrically isolated semiconductor device by depositing a surface layer of dielectric material on a major surface of a monocrystalline substrate, removing portions of the layer to define annular channels, thermally oxidizing the exposed surface areas thereby forming annular ridges of SiO2, removing portions of the dielectric layer, selectively growing an epitaxial silicon layer over the surface wherein the surfaces of the annular ridges of SiO2 and the regions of epitaxial silicon are substantially co-planar. A semiconductor integrated circuit device having a silicon epitaxial layer on a monocrystalline substrate, a network of thermally oxidized silicon regions extending through the epitaxial layer, across the epitaxial layer-substrate interface and into the silicon substrate, the network separating the epitaxial silicon layer into individual pockets, a laterally extending region of low resistivity located generally at the epitaxial layer-substrate interface embodying a first conductivity type impurity, the first type impurity distribution in the epitaxial layer such that the concentration increases with depth.

Abstract translation: 一种通过在单晶衬底的主表面上沉积介电材料的表面层来制造平面介电隔离的半导体器件的方法，去除该层的部分以限定环形通道，热氧化暴露的表面区域，从而形成SiO 2的环形脊， 去除介电层的部分，在表面上选择性地生长外延硅层，其中SiO 2的环形脊的表面和外延硅的区域基本上是共面的。

公开(公告)号：CA1166760A

公开(公告)日：1984-05-01

申请号：CA378808

申请日：1981-06-02

Applicant: IBM

Inventor： GOTH GEORGE R ,  MAGDO INGRID E ,  MALAVIYA SHASHI D

IPC: H01L21/3205 ,  H01L21/033 ,  H01L21/28 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/331 ,  H01L21/336 ,  H01L21/60 ,  H01L29/41 ,  H01L29/417 ,  H01L29/73 ,  H01L29/732 ,  H01L29/78 ,  H01L21/70 ,  H05K3/02 ,  H01L27/02

Abstract: SELF-ALIGNED METAL PROCESS FOR INTEGRATED CIRCUIT METALLIZATION A self-aligned metal process is described which achieves self-aligned metal to silicon contacts and sub-micron contact-to-contact and metal-to-metal spacing. The insulation between the contacts and the metal is a pattern of dielectric material having a thickness dimension in the order of a micron or less. The metal and dielectric structure is substantially planar. The method for forming integrated circuits with this structure involves providing a silicon body and then forming a first insulating layer on a major surface of the silicon body. A layer of polycrystalline silicon is formed thereover. Openings are made in the polycrystalline silicon layer by reactive ion etching which results in the structure having substantially horizontal surfaces and substantially vertical surfaces. A second insulating layer is then formed on both the substantially horizontal surfaces and substantially vertical surfaces. Reactive ion etching of this second insulating layer substantially removes the horizontal layers and provides a narrow dimensioned dielectric pattern of regions on the major surface of the silicon body. The remaining polycrystalline silicon layer is then removed by etching to leave the narrow dimensioned regions on the major surface of the silicon body. A conductive layer is blanket deposited over the narrow dimensioned regions and areas in between. A blanket layer of a plastic material over the conductive layer to planarize the surface is accomplished. Reactive FI9-80-010 ion etching the plastic material and the conductive layer is continued until the tops of the narrow dimensioned regions are reached. The plastic material is then removed leaving the structure of patterns of metal filling the regions between the pattern of dielectric material having a thickness dimension in the order of a micron or less. FI9-80-010

公开(公告)号：CA1063251A

公开(公告)日：1979-09-25

申请号：CA312408

申请日：1978-09-29

Applicant: IBM

Inventor： JOY RICHARD C ,  MAGDO INGRID E ,  PHILLIPS ALFRED JR

IPC: H01L29/78

Abstract: FIELD EFFECT TRANSISTOR HAVING IMPROVED THRESHOLD STABILITY An improved field effect transistor device in a monocrystalline semiconductor body provided with source and drain regions and a gate electrode disposed over the channel between the source and drain regions wherein at least the drain region is formed of a first region where the impurity concentration increases with depth with the peak concentration being spaced inwardly from the major surface, and a second region located within the first region having a peak impurity concentration at the major surface. The drain region structure in operation promotes the current flow between the source and drain to flow deeper in the channel region and spaced from the gate dielectric layer. In the method for forming the field effect transistor, an impurity is introduced into the semiconductor body underlying at least the ultimate drain region, an epitaxial semiconductor layer deposited, and a second impurity region formed over the first region to form the drain contact. In an alternate embodiment of the method for forming a field effect transistor, a first ion implantation is formed in the drain region, such that the peak impurity concentration is located well within the body spaced from the surface thereof, and a second ion implantation, or diffusion, performed forming the source and also the ohmic contact for the drain which is located over the first region and within the first implanted region.

公开(公告)号：CA1048331A

公开(公告)日：1979-02-13

申请号：CA213610

申请日：1974-11-13

Applicant: IBM

Inventor： MAGDO INGRID E ,  MAGDO STEVEN

IPC: H01L29/73 ,  H01L21/00 ,  H01L21/306 ,  H01L21/308 ,  H01L21/331 ,  G03G13/26

Abstract: A METHOD FOR FABRICATING MINUTE OPENINGS IN INTEGRATED CIRCUITS A method in the fabrication of integrated circuits for forming small openings through electrically insulative passivating layers on semiconductor surfaces. First and second layers of different insulative material are formed on the semiconductor surface. Then, a first slot extending through the second or top layer is formed by chemical etching through an etch-resistant mask with an etchant which selectively etches the material in the top layer. The top layer is then covered with a photoresist mask having a second slot which crosses the first slot, and the structure is subjected to chemical etching through the photoresist mask with an etchant that selectively etches the material in the first or bottom layer to, thereby, form a small opening through this bottom layer which is defined by the intersecting portions of the first and second slots.

公开(公告)号：FR2352402A1

公开(公告)日：1977-12-16

申请号：FR7636400

申请日：1976-11-29

Applicant: IBM

Inventor： KWAP THEODORE W ,  MAGDO INGRID E

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/8222 ,  H01L27/07 ,  H01L27/082 ,  H01L29/08 ,  H01L27/00

Abstract: Disclosed is a semiconductor structure with an annular collector/subcollector region. The base area with the emitter, is positioned over the collector/subcollector region only, resulting in a smaller base to collector capacitance. Packing density is improved and circuit design flexibility is provided by the ability to change the emitter size without changing the size of the overall structure.

公开(公告)号：FR2305027A1

公开(公告)日：1976-10-15

申请号：FR7602502

申请日：1976-01-27

Applicant: IBM

Inventor： MAGDO INGRID E ,  MAGDO STEVEN

IPC: H01L27/04 ,  H01L21/331 ,  H01L21/822 ,  H01L29/73 ,  H01L29/8605 ,  H01L29/06

Abstract: A semiconductor resistor structure for providing a high value resistance particularly adapted for space charge limited transistor applications, the resistor being fabricated in a semiconductor body having a resistivity in excess of 1 ohm cm., more preferably in semiconductor material that is nearly intrinsic. The resistor has two parallel elongated surface diffused regions in the body of an impurity similar to the background impurity of the body and having a surface concentration sufficient to provide an ohmic contact, the boundaries of said surface diffused regions defined by the interface where the impurity concentration of the diffused region is ten percent more than the impurity concentration of the background impurity of the body. In a preferred embodiment, the surface diffused regions are spaced such that the boundaries intersect with each other, and ohmic contact terminals to each of the diffused regions.