公开(公告)号：WO2004063834A2

公开(公告)日：2004-07-29

申请号：PCT/GB2004000065

申请日：2004-01-09

Applicant: IBM ,  IBM UK ,  HOLLOWAY LANE THOMAS ,  MALIK NADEEM ,  SAHA AVIJIT

Inventor： HOLLOWAY LANE THOMAS ,  MALIK NADEEM ,  SAHA AVIJIT

IPC: G06F20060101 ,  G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F

CPC classification number: G06F9/3808 ,  G06F9/30156 ,  G06F9/30178

Abstract: A method, apparatus, and computer instructions for processing a s et of instructions in which the set of instructions includes operation codes and operands. A repeating sequence of sequential operation codes within the set of instructions is identified to form an identified sequence of operation codes. The set of instructions is compressed using the identified sequence of operation codes to form a set of compressed instructions for execution by a processor.

Abstract translation: 一种用于处理指令集的方法，装置和计算机指令，其中所述指令集包括操作码和操作数。 识别该组指令内的顺序操作码的重复序列以形成所识别的操作码序列。 使用所识别的操作代码序列来压缩指令集，以形成用于由处理器执行的一组压缩指令。

公开(公告)号：WO2004036457A3

公开(公告)日：2004-06-17

申请号：PCT/GB0304413

申请日：2003-10-10

Applicant: IBM ,  IBM UK

Inventor： DIETZ TIMOTHY ,  KOBROSLY WALID ,  MALIK NADEEM

IPC: G06F17/30

CPC classification number: G06F17/30884

Abstract: The user at a receiving display station is enabled to make an overall scan of a sequence of Web documents developed in a search of the Web, and to select and save hyperlinks that appear to be of potential interest from any or all of the sequence of Web documents. A user is enabled to selectively move hyperlinks from any of a sequence of hypertext documents to a display window to thereby compile a list of hyperlinks having potential interest. The user is then enabled to subsequently select hyperlinks from said list to thereby access the linked hypertext documents; i.e. the user may subsequently, at his convenience, browse through the hyperlinks that he has selected and saved. A window is set aside on the display for the display of the saved hyperlinks.

Abstract translation: 在接收显示台上的用户能够对在Web搜索中开发的Web文档序列进行全面扫描，并且从任意或全部的Web序列中选择并保存看起来可能感兴趣的超链接 文档。 用户能够选择性地将超链接从任何超文本文档序列移动到显示窗口，从而编辑具有潜在兴趣的超链接列表。 然后用户能够随后从所述列表中选择超链接，从而访问链接的超文本文件; 即用户随后可以在他方便的时候浏览他已经选择和保存的超链接。 在显示屏上放置一个窗口，用于显示保存的超链接。

公开(公告)号：JP2007115241A

公开(公告)日：2007-05-10

申请号：JP2006271264

申请日：2006-10-02

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： WALID KOBROSLY ,  MALIK NADEEM ,  TIMOTHY ALAN DIETZ

IPC: G06F13/00

CPC classification number: G06Q10/107 ,  H04L51/066

Abstract: PROBLEM TO BE SOLVED: To provide an effective and practical application, accompanying the exchange of content of an e-mail message and a Web document or a Web page. SOLUTION: A receiving computer controlled display terminal that accesses and displays a network, e.g. Web document, becomes able to select a section of the displayed Web document and to designate, e.g. block off a section in the document and to transform the designated section into an E-mail message. This E-mail message can then be sent to selected terminals on the Web. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供有效和实际的应用程序，伴随电子邮件消息和Web文档或网页的内容交换。 解决方案：接收计算机控制的显示终端，其访问和显示网络，例如， Web文档变得能够选择所显示的Web文档的一部分并且指定，例如， 阻止文档中的一个部分，并将指定的部分转换为电子邮件。 然后可以将此电子邮件发送到Web上的所选终端。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2005149497A

公开(公告)日：2005-06-09

申请号：JP2004323732

申请日：2004-11-08

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： HOLLOWAY LANE T ,  MALIK NADEEM

IPC: G06F12/08 ,  G06F12/12

CPC classification number: G06F12/122 ,  G06F12/0848 ,  G06F12/0875

Abstract: PROBLEM TO BE SOLVED: To provide a cache system capable of continuously caching lines based on use frequency, and of potentially increasing a total hit rate of a cache memory.
SOLUTION: In a preferred embodiment, a DFI-cache (Dynamic Frequent Instruction cache) is queried simultaneously with a main cache, and if a requested address is in either cache, a hit results. The DFI-cache retains frequently used instructions longer than the main cache, so that the main cache can invalidate lines while still enjoying the benefits of a cache hit when next accessing that line.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供能够基于使用频率连续缓存线路并且潜在地增加高速缓冲存储器的总命中率的高速缓存系统。 解决方案：在优选实施例中，与主缓存同时查询DFI缓存（动态频繁指令高速缓存），并且如果请求的地址在任一高速缓存中，则命中结果。 DFI缓存保留长于主缓存的频繁使用的指令，以便主缓存可以使线路无效，同时在下次访问该线路时仍享受缓存命中的好处。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：AU2003269274A1

公开(公告)日：2004-05-04

申请号：AU2003269274

申请日：2003-10-10

Applicant: IBM

Inventor： DIETZ TIMOTHY ,  KOBROSLY WALID ,  MALIK NADEEM

IPC: G06F17/30

Abstract: The user at a receiving display station is enabled to make an overall scan of a sequence of Web documents developed in a search of the Web, and to select and save hyperlinks that appear to be of potential interest from any or all of the sequence of Web documents. A user is enabled to selectively move hyperlinks from any of a sequence of hypertext documents to a display window to thereby compile a list of hyperlinks having potential interest. The user is then enabled to subsequently select hyperlinks from said list to thereby access the linked hypertext documents; i.e. the user may subsequently, at his convenience, browse through the hyperlinks that he has selected and saved. A window is set aside on the display for the display of the saved hyperlinks. Conveniently, the means to selectively move hyperlinks include means for dragging selected hyperlinks from their hypertext documents and dropping the hyperlinks into the display window.

公开(公告)号：CA2511474A1

公开(公告)日：2004-07-29

申请号：CA2511474

申请日：2004-01-09

Applicant: IBM

Inventor： SAHA AVIJIT ,  MALIK NADEEM ,  HOLLOWAY LANE THOMAS

IPC: G06F20060101 ,  G06F9/30 ,  G06F9/318 ,  G06F9/38

Abstract: A method, apparatus, and computer instructions for processing a set of instructions in which the set of instructions includes operation codes and operands. A repeating sequence of sequential operation codes within the set of instructions is identified to form an identified sequence of operation codes . The set of instructions is compressed using the identified sequence of operation codes to form a set of compressed instructions for execution by a processor.

公开(公告)号：DE69622301T2

公开(公告)日：2003-02-20

申请号：DE69622301

申请日：1996-02-21

Applicant: IBM

Inventor： MALIK NADEEM ,  O'KRAFKA BRIAN ,  SAHA AVIJIT ,  SALAMIAN SHAHRAM

IPC: G06F15/16 ,  G06F11/28 ,  G06F12/08 ,  G06F15/177 ,  G06F11/00 ,  G06F9/46

Abstract: A method and system are disclosed for verifying consistency of an instruction execution order of a multiprocessor data processing system 10 with a specified memory consistency model. Each processor 12 within the multiprocessor data processing system executes instructions from an associated one of a number of instruction streams 60, 62, which include instructions that store a number of unique values from multiple processors to a single selected address within memory. One of the unique values is loaded from the selected address to a particular processor within the data processing system. A set of valid values which may be returned by the loading step is determined according to the specified memory consistency model. By comparing the unique value with members of the set of valid values, the instruction execution order of the multiprocessor data processing system is verified. Utilizing the unique value which was returned by the load instruction, the set of valid values may then be updated.

公开(公告)号：DE69622301D1

公开(公告)日：2002-08-22

申请号：DE69622301

申请日：1996-02-21

Applicant: IBM

Inventor： MALIK NADEEM ,  O'KRAFKA BRIAN ,  SAHA AVIJIT ,  SALAMIAN SHAHRAM

IPC: G06F15/16 ,  G06F11/28 ,  G06F12/08 ,  G06F15/177 ,  G06F11/00 ,  G06F9/46

Abstract: A method and system are disclosed for verifying consistency of an instruction execution order of a multiprocessor data processing system 10 with a specified memory consistency model. Each processor 12 within the multiprocessor data processing system executes instructions from an associated one of a number of instruction streams 60, 62, which include instructions that store a number of unique values from multiple processors to a single selected address within memory. One of the unique values is loaded from the selected address to a particular processor within the data processing system. A set of valid values which may be returned by the loading step is determined according to the specified memory consistency model. By comparing the unique value with members of the set of valid values, the instruction execution order of the multiprocessor data processing system is verified. Utilizing the unique value which was returned by the load instruction, the set of valid values may then be updated.