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公开(公告)号:GB2520268A
公开(公告)日:2015-05-20
申请号:GB201319987
申请日:2013-11-13
Applicant: IBM
Inventor: RUF JUERGEN , GREINER CARSTEN , ALLMENDINGER DIRK , MATAYAMBATH ROOPESH AMBALATH
Abstract: The invention is an error injector 212 to be inserted between devices 202/4 connected by a packet communications link and intended to intercept packets traversing that link. The invention is preferably used for testing hardware description language (HDL) designs of systems on chips (SoC). It is preferably applied to packet links using the Peripheral Component Interface Express (PCIe) or Infiniband protocols. The invention randomly selects packets 302 and caches a copy 310 in a buffer. It compares the length of subsequent packets 304/6 with the stored packet and determines whether to replace 308 the subsequent packet with the stored packet 312. Preferably substitution only occurs if both packets have identical lengths. The invention allows validly formatted packets with out of order sequence numbers to be inserted without the need for the error injector to create them. Thereby avoiding CRC generation and similar.
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公开(公告)号:GB2524979A
公开(公告)日:2015-10-14
申请号:GB201406264
申请日:2014-04-08
Applicant: IBM
Inventor: BOEKHOLT SVEN , ALLMENDINGER DIRK , GANFIELD PAUL A , MATAYAMBATH ROOPESH AMBALATH
IPC: G01R31/317 , G01R31/3193 , G06F11/07
Abstract: A method for verifying the functionality of a digital circuit with parallel data transfer paths (PCI express) between a sender with a sender deskew circuit and a receiver with a receiver deskew circuit is provided. The method comprises introducing a skew between the at least two parallel data sequences by erasing or replacing one of the control data packets (S, SKP or SKIP) inserted by the sender deskew circuit (21) or by inserting a further control data packet in one of the at least two parallel data sequences before the receipt by the receiver (22) (S5) and checking whether an expected overflow or underflow indication signal is provided by the receiver or not.
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