公开(公告)号：GB2547159A

公开(公告)日：2017-08-09

申请号：GB201707830

申请日：2015-11-11

Applicant: IBM

Inventor： JOSE EDUARDO MOREIRA ,  ILIE GABRIEL TANASE ,  JESSICA HUI-CHUN TSENG ,  DAVID JOEL EDELSOHN ,  MAURICIO J SERRANO ,  PENG WU

IPC: G06F9/30 ,  G06F15/80

Abstract: Techniques for switching between two (thread and lane) modes of execution in a dual execution mode processor are provided. In one aspect, a method for executing a single instruction stream having alternating serial regions and parallel regions in a same processor is provided. The method includes the steps of: creating a processor architecture having, for each architected thread of the single instruction stream, one set of thread registers, and N sets of lane registers across N lanes; executing instructions in the serial regions of the single instruction stream in a thread mode against the thread registers; executing instructions in the parallel regions of the single instruction stream in a lane mode against the lane registers; and transitioning execution of the single instruction stream from the thread mode to the lane mode or from the lane mode to the thread mode.