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    Processor unit for multiply and accumulate operations
    1.
    发明专利
    Processor unit for multiply and accumulate operations 未知

    公开(公告)号：GB2606908A

    公开(公告)日：2022-11-23

    申请号：GB202209610

    申请日：2020-11-30

    Applicant: IBM

    Inventor： JENTJE LEENSTRA ,  ANDREAS WAGNER ,  JOSE EDUARDO MOREIRA ,  BRIAN WILLIAM THOMPTO

    IPC: G06F9/302

    Abstract: A processor unit for multiply and accumulate ("MAC") operations is provided, the processor unit comprising: a plurality of MAC units for performing a set of MAC operations, wherein each MAC unit of the plurality of MAC units including an execution unit and a one-write one-read ("1W/1R") register file, wherein the 1W/1R register file having at least one accumulator; and another register file, wherein the execution unit of each MAC unit being configured to perform a subset of MAC operations by computing a product of a set of values received from the another register file and adding the computed product to a content of the at least one accumulator, wherein each MAC unit being configured to perform the subset of MAC operations in a single clock cycle.

    Transitioning the processor core from thread to lane mode and enabling data between the two modes
    2.
    发明专利
    Transitioning the processor core from thread to lane mode and enabling data between the two modes 未知

    公开(公告)号：GB2547159A

    公开(公告)日：2017-08-09

    申请号：GB201707830

    申请日：2015-11-11

    Applicant: IBM

    Inventor： JOSE EDUARDO MOREIRA ,  ILIE GABRIEL TANASE ,  JESSICA HUI-CHUN TSENG ,  DAVID JOEL EDELSOHN ,  MAURICIO J SERRANO ,  PENG WU

    IPC: G06F9/30 ,  G06F15/80

    Abstract: Techniques for switching between two (thread and lane) modes of execution in a dual execution mode processor are provided. In one aspect, a method for executing a single instruction stream having alternating serial regions and parallel regions in a same processor is provided. The method includes the steps of: creating a processor architecture having, for each architected thread of the single instruction stream, one set of thread registers, and N sets of lane registers across N lanes; executing instructions in the serial regions of the single instruction stream in a thread mode against the thread registers; executing instructions in the parallel regions of the single instruction stream in a lane mode against the lane registers; and transitioning execution of the single instruction stream from the thread mode to the lane mode or from the lane mode to the thread mode.

    Locking power supplies
    4.
    发明专利
    Locking power supplies 未知

    公开(公告)号：GB2541333A

    公开(公告)日：2017-02-15

    申请号：GB201620508

    申请日：2015-05-19

    Applicant: IBM

    Inventor： JOSE EDUARDO MOREIRA ,  HAROLD WADE CAIN III ,  DAVID DALY

    IPC: G06F1/18 ,  H05K7/14

    Abstract: There is provided an apparatus, a method and computer program product for managing one or more components of an electronic machine. A user connects one or more components to an electronic machine in parallel. The electronic machine determines whether the components are failed. A latch device, attached to each component, automatically locks one or more of the components to the electronic machine if the one or more of the components are not failed. The electromechanical latch automatically releases the one or more of the components from the electronic machine if the one or more of the components are failed.

    Instruction handling for accumulation of register results in a microprocessor
    5.
    发明专利
    Instruction handling for accumulation of register results in a microprocessor 未知

    公开(公告)号：GB2603653A

    公开(公告)日：2022-08-10

    申请号：GB202202229

    申请日：2020-07-21

    Applicant: IBM

    Inventor： BRIAN THOMPTO ,  MAARTEN BOERSMA ,  ANDREAS WAGNER ,  JOSE EDUARDO MOREIRA ,  HUNG LE ,  SILVIA MELITTA MUELLER ,  DUNG NGUYEN

    IPC: G06F9/30

    Abstract: A computer system, processor, and method for processing information is disclosed that includes at least one computer processor; a main register file associated with the at least one processor, the main register file having a plurality of entries for storing data, one or more write ports to write data to the main register file entries, and one or more read ports to read data from the main register file entries; one or more execution units including a dense math execution unit; and at least one accumulator register file having a plurality of entries for storing data. The results of the dense math execution unit in an aspect are written to the accumulator register file, preferably to the same accumulator register file entry multiple times, and the data from the accumulator register file is written to the main register file.

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