公开(公告)号：CA2068010C

公开(公告)日：1996-10-22

申请号：CA2068010

申请日：1992-05-05

Applicant: IBM

Inventor： ENG ROBERT CHIH-TSIN ,  GALELLA JOHN WALTER ,  MCCRARY REX ELDON ,  MCDONALD MARK GEHRES ,  STELZER ERIC HENRY ,  YENTZ FREDERICK CHARLES

IPC: G06F13/00 ,  G06F13/28 ,  G06F13/36 ,  G06F13/362 ,  G06F13/14

Abstract: Methods and apparatus are set forth which optimize and balance the use of processor card (or complex) resources (e. g., memory, the local bus, etc .), with the use of other system resources, such as the card to card communications bus and devices attached thereto, in dual bus computing systems. A new data rate management technique reduces data transfer overhead particularly for burst mode transfers. The invention promptly services pending memory refresh requests; limits multiple accesses to on card (or processor complex) memory by an Alternate Bus Master to a predetermined number of cycles where the processor requests the use of its local bus; and allows an Alternate Bus Master unlimited accesses to the processor local bus when the Alternate Bus Master owns the card to card communications bus and the processor subsequently requests that bus. The aforementioned balance of resources is achieved using a Bus Hold On Grant ("BSHOG") scheduling procedure which, assuming a bursting Alternate Bus Master has gained control of the local processor bus and is conducting data transfer cycles when the processor requests the local bus, allows the Alternate Bus Master to conditionally retain local bus ownership over a plurality of Alternate Bus Master data transfer cycles.