公开(公告)号：JPH11175491A

公开(公告)日：1999-07-02

申请号：JP24160698

申请日：1998-08-27

Applicant: IBM

Inventor： ANDREWS LAWRENCE P ,  BECKMAN RICHARD CLYDE ,  ENG ROBERT CHIH-TSIN ,  LINGER JUDITH MARIE ,  PETTY JOSEPH C JR ,  SINIBALDI JOHN CLAUDE ,  TURBEVILLE GARY L ,  WILLIAMS KEVIN BRADLEY

IPC: G06F15/16 ,  G06F13/00 ,  G06F13/24 ,  G06F15/177 ,  H04L12/66 ,  G06F15/163

Abstract: PROBLEM TO BE SOLVED: To distribute the operation that processes transmission data of a primary speed by making a host processor read information from 2nd data memory when an interrupt is received. SOLUTION: Although 16-bits in a HBRIDGE interrupt register are usually used to represent different types of services up to sixteen, a digital signal processor(DSP) 12 sends a control block of data that represents an interrupt to be requested to a prescribed area in data memory of a controller card 4 by direct memory access process. Therefore, DSP subsystems 12 set a certain bit to send an interrupt through PCI buses 48 and 53. When the interrupt is received through an interrupt A line, a controller processor 53a decides that a DSP subsystem 12-0 requested the interrupt, and when the interrupt is received through an interrupt B line, it decides that one of DSPs 12-1 to 12-7 requested it.

公开(公告)号：DE69219848D1

公开(公告)日：1997-06-26

申请号：DE69219848

申请日：1992-08-10

Applicant: IBM

Inventor： ENG ROBERT CHIH-TSIN ,  GALELLA JOHN WALTER ,  MCCARARY REX ELDON ,  MCDONALD MARK GEHRES ,  STELZER ERIC HENRY ,  YENTZ FREDERICK CHARLES

IPC: G06F13/00 ,  G06F13/28 ,  G06F13/36 ,  G06F13/362

Abstract: Methods and apparatus are set forth which optimize and balance the use of processor card (or complex) resources (e.g., memory, the local bus, etc.), with the use of other system resources, such as the card to card communications bus and devices attached thereto, in dual bus computing systems. A new data rate management technique reduces data transfer overhead particularly for burst mode transfers. The invention promptly services pending memory refresh requests; limits multiple accesses to on card (or processor complex) memory by an Alternate Bus Master to a predetermined number of cycles where the processor requests the use of its local bus; and allows an Alternate Bus Master unlimited accesses to the processor local bus when the Alternate Bus Master owns the card to card communications bus and the processor subsequently requests that bus. The aforementioned balance of resources is achieved using a Bus Hold On Grant ("BSHOG") scheduling procedure which, assuming a bursting Alternate Bus Master has gained control of the local processor bus and is conducting data transfer cycles when the processor requests the local bus, allows the Alternate Bus Master to conditionally retain local bus ownership over a plurality of Alternate Bus Master data transfer cycles.

公开(公告)号：CA2068010C

公开(公告)日：1996-10-22

申请号：CA2068010

申请日：1992-05-05

Applicant: IBM

Inventor： ENG ROBERT CHIH-TSIN ,  GALELLA JOHN WALTER ,  MCCRARY REX ELDON ,  MCDONALD MARK GEHRES ,  STELZER ERIC HENRY ,  YENTZ FREDERICK CHARLES

IPC: G06F13/00 ,  G06F13/28 ,  G06F13/36 ,  G06F13/362 ,  G06F13/14

Abstract: Methods and apparatus are set forth which optimize and balance the use of processor card (or complex) resources (e. g., memory, the local bus, etc .), with the use of other system resources, such as the card to card communications bus and devices attached thereto, in dual bus computing systems. A new data rate management technique reduces data transfer overhead particularly for burst mode transfers. The invention promptly services pending memory refresh requests; limits multiple accesses to on card (or processor complex) memory by an Alternate Bus Master to a predetermined number of cycles where the processor requests the use of its local bus; and allows an Alternate Bus Master unlimited accesses to the processor local bus when the Alternate Bus Master owns the card to card communications bus and the processor subsequently requests that bus. The aforementioned balance of resources is achieved using a Bus Hold On Grant ("BSHOG") scheduling procedure which, assuming a bursting Alternate Bus Master has gained control of the local processor bus and is conducting data transfer cycles when the processor requests the local bus, allows the Alternate Bus Master to conditionally retain local bus ownership over a plurality of Alternate Bus Master data transfer cycles.

公开(公告)号：DE69219848T2

公开(公告)日：1997-10-23

申请号：DE69219848

申请日：1992-08-10

Applicant: IBM

Inventor： ENG ROBERT CHIH-TSIN ,  GALELLA JOHN WALTER ,  MCCARARY REX ELDON ,  MCDONALD MARK GEHRES ,  STELZER ERIC HENRY ,  YENTZ FREDERICK CHARLES

IPC: G06F13/00 ,  G06F13/28 ,  G06F13/36 ,  G06F13/362

Abstract: Methods and apparatus are set forth which optimize and balance the use of processor card (or complex) resources (e.g., memory, the local bus, etc.), with the use of other system resources, such as the card to card communications bus and devices attached thereto, in dual bus computing systems. A new data rate management technique reduces data transfer overhead particularly for burst mode transfers. The invention promptly services pending memory refresh requests; limits multiple accesses to on card (or processor complex) memory by an Alternate Bus Master to a predetermined number of cycles where the processor requests the use of its local bus; and allows an Alternate Bus Master unlimited accesses to the processor local bus when the Alternate Bus Master owns the card to card communications bus and the processor subsequently requests that bus. The aforementioned balance of resources is achieved using a Bus Hold On Grant ("BSHOG") scheduling procedure which, assuming a bursting Alternate Bus Master has gained control of the local processor bus and is conducting data transfer cycles when the processor requests the local bus, allows the Alternate Bus Master to conditionally retain local bus ownership over a plurality of Alternate Bus Master data transfer cycles.

公开(公告)号：DE69836307T2

公开(公告)日：2007-04-26

申请号：DE69836307

申请日：1998-09-15

Applicant: IBM

Inventor： ANDREWS LAWRENCE P ,  BECKMAN RICHARD CLYDE ,  ENG ROBERT CHIH-TSIN ,  LINGER JUDITH MARIE ,  PETTY JOSEPH C ,  SINIBALDI JOHN CLAUDE ,  TURBEVILLE GARY L ,  WILLIAMS KEVIN BRADLEY

IPC: G06F13/24 ,  G06F15/16 ,  G06F13/00 ,  G06F15/177 ,  H04L12/66

Abstract: A pair of communications adapters each include a number of digital signal processors (12) and network interface circuits (24) for the attachment of a multi-channel telephone line. A bus connecting the communications adapters can carry data between a network line attached to one of the adapters and the digital signal processors of the other adapter. The digital signal processors on each card are connected to a host, or controller, processor (2). Each digital signal processor interrupts its host processor by transmitting an interrupt control block as data to a data memory of the host processor, and by subsequently sending an interrupt causing the host processor to examine the data memory. Preferably, the interrupt control block includes data representing a number of requested interrupts.

公开(公告)号：DE69836307D1

公开(公告)日：2006-12-14

申请号：DE69836307

申请日：1998-09-15

Applicant: IBM

Inventor： ANDREWS LAWRENCE P ,  BECKMAN RICHARD CLYDE ,  ENG ROBERT CHIH-TSIN ,  LINGER JUDITH MARIE ,  PETTY JOSEPH C ,  SINIBALDI JOHN CLAUDE ,  TURBEVILLE GARY L ,  WILLIAMS KEVIN BRADLEY

IPC: G06F13/24 ,  G06F15/16 ,  G06F13/00 ,  G06F15/177 ,  H04L12/66

Abstract: A pair of communications adapters each include a number of digital signal processors (12) and network interface circuits (24) for the attachment of a multi-channel telephone line. A bus connecting the communications adapters can carry data between a network line attached to one of the adapters and the digital signal processors of the other adapter. The digital signal processors on each card are connected to a host, or controller, processor (2). Each digital signal processor interrupts its host processor by transmitting an interrupt control block as data to a data memory of the host processor, and by subsequently sending an interrupt causing the host processor to examine the data memory. Preferably, the interrupt control block includes data representing a number of requested interrupts.