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    Multi-phase CCD shift register optical sensor with high resolution
    2.
    发明授权
    Multi-phase CCD shift register optical sensor with high resolution 失效
    具有高分辨率的多相CCD移位寄存器光学传感器

    公开(公告)号：US3909803A

    公开(公告)日：1975-09-30

    申请号：US30316372

    申请日：1972-11-02

    Applicant: IBM

    Inventor： BANKOWSKI JR WALTER F ,  KUMAR VIJAY R ,  MCGOVERN WILLIAM ,  TARTAMELLA JOHN D

    IPC: G11C27/04 ,  H01L27/148 ,  G11C11/42 ,  G11C11/40 ,  G11C19/28

    CPC classification number: H01L27/14831 ,  G11C27/04 ,  H04N5/37213

    Abstract: This specification describes a scheme for improving the optical resolution of charge coupled device (CCD) shift registers by permitting optical sensing in potential wells under adjacent or closely spaced gates. First one gate in each of the bits of the shift register is energized for optical sensing and the information so sensed is read out of the shift register and stored in memory of some kind. Thereafter, an adjacent or closely spaced gate is energized to sense data optically and this information is read out of the shift register and stored. This is continued until all of the possible gates, or as many as desired, are used for optical sensing. When optical sensing is complete the stored data is reorganized by an interleaving procedure that leaves the data in coherent form.

    Abstract translation: 本说明书描述了一种用于通过允许在相邻或紧密间隔的栅极的势阱中的光学感测来改善电荷耦合器件（CCD）移位寄存器的光学分辨率的方案。 移位寄存器的每个位中的第一个门被激励用于光学感测，并且如此感测的信息从移位寄存器读出并存储在某种存储器中。 此后，相邻或间隔相近的门被激励以光学地读取数据，并将该信息从移位寄存器中读出并被存储。 这一直持续到所有可能的栅极，或者根据需要被用于光学感测。 当光学感测完成时，存储的数据通过以相干形式离开数据的交织过程进行重组。

    Arithmetic and logic system using ac and dc signals
    3.
    发明授权
    Arithmetic and logic system using ac and dc signals 失效
    使用交流和直流信号的算术和逻辑系统

    公开(公告)号：US3505648A

    公开(公告)日：1970-04-07

    申请号：US3505648D

    申请日：1966-09-28

    Applicant: IBM

    Inventor： MCGOVERN WILLIAM ,  PETERSEN DAVID A ,  ROSS RALPH D

    IPC: G06F7/57 ,  G06F9/302 ,  G06F9/315 ,  G06F9/40 ,  G06F15/78 ,  G06F1/00 ,  G06F7/00 ,  G06F15/00 ,  G11B13/00

    CPC classification number: G06F9/4425 ,  G06F7/483 ,  G06F7/57 ,  G06F9/3001 ,  G06F9/30032 ,  G06F15/78

    Abstract: 1,163,462. Data processing; data storage registers. INTERNATIONAL BUSINESS MACHINES CORP. 22 Aug., 1967 [28 Sept., 1966], No. 38671/67. Headings G4A and G4C. [Also in Division H3] In data processing apparatus, a register has a plurality of binary stages, a common set input and a common reset input, and is arranged so that data entered therein can be EXCL-ORed with data already in the register. General.-Fig. 1 shows storage STG (addressed by either of two registers SAR), registers SDR, AX, A, C, B, BX, a carry generator CLA, a straight-cross unit which passes one, both or neither halves of a word in SDR, interchanged or not, except that when passing neither half (quiescent state) the output is all ones, and a "funnel" which simply passes the signals on a selected one of its input busses to its output buss. Registers.-Fig. 2 shows a bi-stable trigger 50 with D.C. set and reset inputs applied via diodes 64, 65, and A.C. set and reset inputs applied through capacitors 66, 76, 71, 78 and diodes 67, 75, 72, 79 subject to D.C. gating signals applied through resistors 68, 69, 77, 73, 74, 80. Figs. 3, 7 show the trigger 50 applied to representative stages of the A and B registers respectively, similar arrangements being provided for other registers, so that the following may be achieved by respective control signals: D.C. reset A register to all zeros, invert each bit in A register, interchange contents of A and AX registers, OR funnel output into A register, D.C. set B and C registers to all ones, D.C. reset B and C registers to all zeros, EXCL-OR funnel output into B register (viz. a 1 bit inverts the current bit), shift B register 1 to 4 bit-positions to left or right, interchange contents of B and BX registers, EXCL-OR funnel output into C register, copy contents of B register into C register, D.C. reset AX register to all zeros. Fig. 7 shows the funnel bit gated into each side of the B register stage under control (inter alia) of the opposite output of the stage, but in the case of the C register, the corresponding control is provided from the corresponding stage of the B register. Addition and subtraction.-The A register is reset to all zeros. The B and C registers are reset to all zeros for addition or all ones for subtraction. One operand is passed from storage STG via the register SDR and the funnel and then ORed into the A register and EXCL-ORed into the B and C registers (so that the A register holds the operand, and the B and C registers hold the operand or its ones-complement in the cases of addition and subtraction respectively). The other operand is then similarly passed from storage STG and EXCL-ORed into the B and C registers to form the half-sums of the two operands. The first operand in the A register and the half-sum in the C register are combined in the carry generator CLA which provides carries which are passed via the funnel and EXCL-ORed into the B register which then holds the final sum or difference. In the case of subtraction, the extra one required is provided by a low-order carry inserted into the carry generator CLA. Details of carry generator CLA.-Fig. 18 shows production of carries at bit positions 31-27, the arrangement being repeated for other groups of bit positions. The A register provides one operand and the C register provides the half-sum bits of the two operands. Logical operations.-The OR, AND or EXCL- OR of two operands is obtained in the B register as follows. The A, B and C registers are reset to all zeros. One operand (from the funnel) is ORed into the A register and EXCL-ORed into the B register. If the OR is required, the second operand is ORed into the A register, the B (and C) registers are reset to all zeros, and the contents of the A register are passed via the funnel and EXCL-ORed into the B register. If the EXCL-OR is required, the second operand is ORed into the A register (result not used) and EXCL-ORed into the B register. If the AND is required, the second operand is ORed into the A register and EXCL-ORed into the B register after which the contents of the A register are EXCL-ORed into the B register. Branch on count.-During instruction readout, the B register was set with the branch address and the BX register was set to all ones. The A register is reset to all zeros. The contents of the B and BX registers are interchanged. The all ones in the B register is copied into the C register. The count factor from storage is ORed into the A register and EXCL-ORed into the B and C registers and the output of the carry generator CLA is EXCL-ORed into the B register which thus holds the count factor decremented by one (since the all ones used is the twos-complement of one) and if this indicates that the branch is to take place, the branch address in the BX register is loaded into the instruction counter IC.

    8.
    发明专利
    未知

    公开(公告)号：DE1224542B

    公开(公告)日：1966-09-08

    申请号：DEJ0027184

    申请日：1964-12-22

    Applicant: IBM

    Inventor： MCGOVERN WILLIAM

    IPC: G06F11/267

    Abstract: 1,070,421. Checking arrangements. INTERNATIONAL BUSINESS MACHINES CORPORATION. Nov. 26, 1964 [Dec. 23, 1963], No. 48026/64. Heading G4A. In a cyclically operable computer, a number of error checking circuits are themselves checked during each cycle by application of check test signals which simulate the erroneous signal combinations which the error checking circuits are adapted to recognise, there being means responsive only to an error signal from all of said error checking circuits to set an indicating circuit. The subject matter is included in Specifications 1,070,423 and 1,070,424 which are referred to.

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